Elementary Cell Charge Pump Gate Control

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Solution Overview

Problem

Existing charge pump circuits in integrated circuits face inefficiencies in charge transfer due to imperfect transistor state changes, particularly in PMOS-based designs that require complex well structures and suffer from reduced conduction thresholds.

Innovation Solution

A novel elementary pumping cell design where the gate terminal of the first transistor is connected to the gate terminal of the second transistor, enhancing the control over source/well voltage and improving charge transfer efficiency, utilizing only P-type transistors to eliminate the need for triple-well semiconductor doping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PMOS-based charge pump circuits are used, then the conduction threshold is reduced, but the transistor state changes become imperfect and charge transfer efficiency decreases

Engineering Contradiction:

Improvecharge transfer efficiencyVSAvoidtransistor state control

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A control node is introduced as an intermediary between the clock signal and the transistor gates. This control node receives the clock signal and generates optimized control signals that properly sequence the switching of transistors in the charge pump circuit, ensuring perfect state changes and efficient charge transfer while maintaining the benefits of PMOS-based design.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The control signals applied to the transistor gates are made dynamic and sequential rather than simultaneous. The control node generates time-staggered control signals that dynamically adjust the switching sequence of transistors, ensuring that each transistor transitions to its correct state at the optimal moment, thereby resolving the issue of imperfect state changes.

Inventive Principle:

Principle #15Dynamics

2Reliability

If triple-well semiconductor doping is used to improve transistor control, then the conduction threshold is optimized, but the production complexity increases

Engineering Contradiction:

Improvetransistor controlVSAvoidproduction process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the need for complex triple-well semiconductor doping (a manufacturing-process-based solution) with a circuit-level control mechanism. The control node and its signal generation logic provide the necessary transistor control through electrical signals rather than requiring complex physical doping structures, thereby simplifying the manufacturing process while maintaining or improving transistor control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Instead of changing the physical doping parameters of the semiconductor structure (which would require triple-well processes), the patent changes the electrical control parameters by introducing a control node that generates optimized gate voltages and timing sequences. This parameter change at the circuit level achieves better transistor control without complicating the manufacturing process.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the overall efficiency of the charge pump by ensuring better control over transistor state changes and charge transfer, simplifying production and operation without the need for complex well structures.

Implementation Method 1

a first capacitor C1 comprising a first terminal connected to the clock terminal H and a second terminal

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a second transistor A2 comprising a first source/drain terminal coupled to the output terminal S of the elementary cell, a second source/drain terminal coupled to the input terminal E and a gate terminal coupled to the second terminal of the first capacitor C1

Methodology Applied

Scientific EffectBody effect:

Data Source

PatentUS10910945B2Elementary cell and charge pumps comprising such an elementary cell

Publication Date: 2021.02.02 EM MICROELECTRONIC-MARIN

AI summary

The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.