Elementary Check Node Processing for Non-Binary LDPC Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing architectures for check node processing units in iterative decoders, particularly in non-binary LDPC codes, face high computational complexity and resource requirements, limiting their efficiency and adaptability, especially in high-order Galois fields and high coding rates.
Innovation Solution
A check node processing unit is designed to receive multiple input messages, calculate syndromes using elementary check node processors, and select output messages by identifying distinct symbols with reduced redundancy, leveraging a syndrome calculator, decorrelation unit, and selection unit to minimize computational complexity and hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing architectures for check node processing units are used in iterative decoders for non-binary LDPC codes, then decoding functionality is provided, but computational complexity and resource requirements are high
Solution Approach 1:
The check node processing unit is divided into multiple elementary check node processors, each handling a subset of input messages. This segmentation allows parallel processing of different message subsets, reducing the computational burden on each individual processor while maintaining overall decoding functionality. The syndromes are computed in parallel across multiple processors rather than sequentially in a single unit.
Solution Approach 2:
The patent introduces a new dimension of parallelism by processing multiple syndromes simultaneously through multiple elementary check node processors. Instead of computing syndromes sequentially for each input message combination, the system computes multiple syndromes in parallel by distributing the computation across multiple processing units, thereby increasing throughput without proportionally increasing per-unit complexity.
2Device complexity
If existing check node processing architectures are implemented, then decoding is performed, but hardware implementation costs and silicon area are high
Solution Approach 1:
The hardware architecture is segmented into multiple simple elementary check node processors rather than one complex processor. Each processor has a simplified structure that handles a specific subset of computations, reducing the silicon area and hardware cost per processor. The distributed architecture achieves the same decoding performance through coordinated operation of multiple simpler units.
Solution Approach 2:
Multiple copies of the elementary check node processor are instantiated in parallel, each performing the same simplified function on different input data subsets. This copying approach allows the system to achieve high throughput and maintain decoding performance while keeping each individual processor simple and cost-effective, avoiding the need for a single complex high-cost processor.
3Productivity
If traditional check node processing is used, then syndrome computation is performed, but the number of operations and processing time are high
Solution Approach 1:
The processing of input messages is segmented across multiple elementary check node processors operating in parallel. Each processor handles a subset of the syndrome computations simultaneously, dividing the total processing time among multiple units. This parallel segmentation directly increases throughput by performing multiple syndrome computations at the same time rather than sequentially.
Solution Approach 2:
The multiple elementary check node processors operate continuously and simultaneously on different subsets of input messages, maintaining continuous useful action across the entire processing unit. There is no idle time between processing different syndrome computations since multiple processors are working in parallel throughout the decoding process, maximizing resource utilization and reducing overall processing time.
Data Source
AI summary
At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to generate at least one output message. A syndrome calculator is configured to determine a set of syndromes from the at least three input messages using at least two elementary check node processors. A decorrelation unit is configured to determine, in association with at least an output message, a set of candidate components from the set of syndromes. A selection unit is configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with the at least an output message.