Elevating Circuit Nodes for Backside Power Debugging
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Solution Overview
Problem
The challenge in further reducing the size and increasing scalability of integrated circuits (ICs) lies in the limitations imposed by interconnects, particularly the increased resistance of copper in smaller interconnects, which hampers electron flow and overall IC performance. Additionally, backside power delivery techniques face difficulties in debugging and verification due to obstructions between sensor tools and interconnects, making it hard to accurately measure signal and power interconnects.
Innovation Solution
The solution involves modifying circuit designs to elevate selected circuit nodes, allowing them to be positioned closer to sensor tools for accurate measurement and debugging. This is achieved by modifying the circuit layout to place elevated interconnects within the n closest layers to the signal sensor circuitry, ensuring that critical signals and power interconnects can be accurately measured, even in backside power delivery configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect size is reduced to increase IC scalability, then more components can be implemented per unit area, but interconnect resistance increases which hampers electron flow and IC performance
Solution Approach 1:
The patent introduces a vertical dimension to interconnect routing by elevating selected circuit nodes to higher layers above the transistor layer. This allows signal interconnects to bypass the resistive copper interconnects in lower layers, reducing resistance while maintaining compact IC footprint through three-dimensional stacking.
2Power
If backside power delivery techniques are used to improve power delivery, then power can be delivered to upper layers, but debugging and verification become difficult due to obstructions between sensor tools and interconnects
Solution Approach 1:
The patent applies local quality by selectively elevating only specific circuit nodes (such as power nodes and test nodes) to higher layers while leaving other nodes in their original positions. This allows improved power delivery and easier measurement at elevated nodes without requiring complete redesign of the entire interconnect structure.
Solution Approach 2:
The patent incorporates test nodes and measurement points in elevated layers during the initial circuit design phase, before fabrication. This preliminary placement ensures that sensor tools can access and measure signals without requiring post-fabrication modifications or complex disassembly procedures.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes; identifier circuitry to: identify a node within the plurality of nodes for elevation; and identify a layer of an integrated circuit; port adder circuitry to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer; connector circuitry to modify the circuitry logic by connecting the signal port to the identified node; and layout planner circuitry to determine a layout of the integrated circuit based on the modified circuitry logic.