Elevated Drain Termination for High-Power Transistors

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Solution Overview

Problem

High power transistors with increased unit cell density face breakdown issues due to insufficient gate-to-drain spacing at drain finger electrode ends, leading to unreliable high breakdown voltage performance.

Innovation Solution

The implementation of non-coplanar drain finger termination with curved or tapered ends having increased radius of curvature and extended gate-to-drain spacing, reducing termination electric fields and enhancing breakdown voltage reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If unit cell density is increased to meet higher power requirements, then power capability is improved, but gate-to-drain spacing becomes insufficient leading to reduced breakdown voltage reliability

Engineering Contradiction:
Improvepower capabilityVSAvoidbreakdown voltage reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The drain finger termination is elevated from the coplanar plane to a higher dimension by forming it over a dielectric layer. This vertical dimensionality change allows the termination to be positioned above the gate-to-drain spacing plane, effectively increasing the electrical spacing without occupying additional lateral space, thus resolving the contradiction between high power density and breakdown voltage reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

A dielectric layer is introduced as an intermediary between the drain finger electrode body and the drain finger termination. This intermediary structure enables the termination to be elevated and electrically isolated, providing enhanced gate-to-drain spacing and improving breakdown voltage reliability while maintaining compact device footprint

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If gate-to-drain spacing is extended to improve breakdown voltage, then reliability is improved, but device area increases reducing unit cell density

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of extending gate-to-drain spacing in the lateral plane which would increase device area, the solution elevates the drain finger termination vertically above the gate-to-drain spacing plane. This uses the third dimension to achieve enhanced spacing without lateral expansion, maintaining high unit cell density while improving breakdown voltage

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If drain finger termination is made coplanar with main body, then manufacturing is simple, but termination electric fields are high causing breakdown issues

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidtermination electric fields
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The drain finger termination is elevated vertically above the coplanar plane by forming it over a dielectric layer. This vertical separation reduces the concentration of termination electric fields at the drain finger ends while maintaining manufacturing feasibility through standard semiconductor fabrication processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dielectric layer acts as an intermediary structure that elevates the drain finger termination, thereby reducing termination electric fields. This intermediary approach manages the harmful electric field concentration without significantly complicating the manufacturing process

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9564498B2Transistor with elevated drain termination
Publication Date: 2017.02.07 INFINEON TECHNOLOGIES AMERICAS CORP
  • US9564498B2 patent drawing
  • US9564498B2 patent drawing
  • US9564498B2 patent drawing

AI summary

According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.