Elevated Gate Structure for Lower Parasitic Capacitance in DRAM
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Solution Overview
Problem
As DRAM devices are scaled down, parasitic capacitance and parasitic resistance become significant, leading to diminished device performance and short-channel effects that hinder the gate's control over the channel region, causing variations in electronic characteristics.
Innovation Solution
A semiconductor device is designed with a gate structure elevated on a substrate, reducing the height of the gate conductive layer while maintaining the total gate structure height, which decreases parasitic capacitance and increases effective channel length, mitigating short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the gate conductive layer height is reduced to decrease parasitic capacitance, then parasitic capacitance is decreased, but the gate structure total height must be maintained
Solution Approach 1:
The patent applies dimensionality change by elevating the gate conductive layer from the substrate surface to a higher position using a dielectric layer. This vertical displacement reduces the height of the gate conductive layer relative to the substrate, thereby decreasing parasitic capacitance, while the overall gate structure height is maintained through the combined thickness of the dielectric layer and the elevated gate conductive layer.
2Reliability
If the channel length is increased to mitigate short-channel effect, then short-channel effect is mitigated, but device scaling is limited
Solution Approach 1:
The patent uses dimensionality change to elevate the gate conductive layer, which increases the effective channel length by extending the gate control region vertically. This allows for better gate control over the channel region and mitigation of short-channel effects without requiring a proportional increase in the horizontal channel length, thus enabling continued device scaling.
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a first surface and a second surface protruding from the first surface of the substrate; a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate, and contacting the substrate and the gate oxide layer.