Elevated Gate Structure for DRAM Short-Channel Control
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Solution Overview
Problem
As DRAM devices are scaled down, parasitic capacitance and resistance become significant, leading to diminished device performance and short-channel effects that hinder the gate's control over the channel region, causing variations in electronic characteristics.
Innovation Solution
A semiconductor device with a gate structure elevated on a substrate's elevated portion, reducing the height of the gate conductive layer while maintaining the total gate structure height, thereby decreasing parasitic capacitance and increasing effective channel length to mitigate short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device is scaled down to reduce size, then device dimensions are reduced, but parasitic capacitance and resistance increase leading to diminished performance
Solution Approach 1:
The patent introduces a vertical dimension by forming an elevated portion (fin structure) on the substrate. The gate structure is positioned on this elevated portion, creating a three-dimensional configuration. This dimensional change allows the channel length to be effectively increased in the vertical direction while maintaining reduced planar dimensions, thereby scaling down the device footprint without proportionally increasing parasitic effects.
Solution Approach 2:
The patent creates a localized elevated region with different geometric properties than the surrounding substrate. The elevated portion has increased height and different surface area characteristics, which locally modifies the electrical field distribution and reduces parasitic capacitance in the channel region while maintaining overall device miniaturization.
2Length of moving object
If the channel length is reduced to scale down the device, then device size decreases, but short-channel effects increase reducing gate control
Solution Approach 1:
The patent compensates for reduced planar channel length by utilizing the vertical dimension through the elevated portion structure. The gate extends along the elevated portion, creating an effective channel length that includes both horizontal and vertical components. This allows the device to maintain adequate gate control over the channel even when the planar channel length is reduced for scaling.
Solution Approach 2:
The channel region is segmented into different zones: the elevated portion with enhanced gate control and the surrounding substrate regions. This segmentation allows the critical channel region to have extended effective length through the vertical structure, while other regions can be minimized for scaling, thus maintaining gate control without uniformly increasing all dimensions.
3Object-affected harmful factors
If the gate conductive layer height is reduced to decrease parasitic capacitance, then parasitic capacitance decreases, but the total gate structure height must be maintained for functionality
Solution Approach 1:
The patent shifts the gate structure to be positioned on the elevated portion rather than directly on the substrate surface. This repositioning in the vertical dimension allows the gate conductive layer to have reduced height (decreasing parasitic capacitance) while the elevated portion provides the necessary structural support and electrical isolation, maintaining the functional gate structure height through the combination of elevated portion height and reduced gate layer height.
Solution Approach 2:
The elevated portion acts as an intermediary structure between the substrate and the gate conductive layer. It provides mechanical support and electrical isolation, enabling the gate conductive layer to be thinner (reducing parasitic capacitance) while the overall gate structure maintains sufficient height through the elevated portion's contribution to the total structure height.
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion and a gate conductive layer disposed on the dielectric layer.