Elevated Source Drain Layers for SOI and Bulk MISFETs
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Solution Overview
Problem
The miniaturization of MISFETs leads to short channel effects and increased external resistance due to the thin SOI layer, and the formation of elevated source and drain structures is complicated by varying impurity concentrations, affecting the thickness of elevated layers in both SOI-MISFET and bulk-MISFET, which can result in improper silicidation and increased contact resistance.
Innovation Solution
Optimizing the thickness of elevated layers for both SOI-MISFET and bulk-MISFET by adjusting impurity concentrations in selective epitaxial growth, ensuring the elevated layer of the SOI-MISFET is higher than the gate to prevent silicide layer contact with the buried insulating layer, and using a thicker gate insulator for bulk-MISFET to achieve higher breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SOI layer is made thin to achieve full depletion and steep sub-threshold factor, then the threshold voltage control is improved, but the external resistance of the MISFET increases
Solution Approach 1:
The patent elevates the source and drain regions from the same plane as the gate to a higher dimension by forming elevated layers on top of the SOI layer. This vertical stacking allows the source/drain to be positioned above the gate level, preventing the silicide layer from contacting the buried insulating layer while maintaining low external resistance through proper silicide formation on the elevated regions.
2Manufacturing precision
If elevated source and drain structure is formed to reduce external resistance, then the contact resistance is reduced, but the breakdown voltage between source and drain deteriorates
Solution Approach 1:
The patent applies different structural configurations to different regions of the device. The elevated source and drain regions are formed with specific thicknesses and impurity concentrations tailored to each region's requirements, allowing optimization of contact resistance in the elevated regions while maintaining breakdown voltage through appropriate doping profiles and structural design.
3Productivity
If SOI substrate is used for high-performance MISFET, then the integration density is improved, but the breakdown voltage is reduced limiting voltage regime
Solution Approach 1:
The patent segments the device into different regions with different substrate types - SOI regions for high-performance, low-voltage MISFETs and bulk regions for high-breakdown voltage elements. This segmentation allows each region to be optimized for its specific function while sharing the same substrate, achieving both high integration density and high breakdown voltage capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher integration and performance of semiconductor devices with reduced external resistance and improved breakdown voltage, enabling the simultaneous fabrication of high-performance SOI-MISFET and bulk-MISFET on the same substrate without complicating the process.
Implementation Method 1
by using a selective epitaxial growth method, the silicide layer is prevented from reaching up to the buried insulating layer
Data Source
AI summary
There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.