Elevated Source Contact Structure for Latch-Up Rugged Power Semiconductors
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Solution Overview
Problem
Power semiconductor devices face challenges in achieving high reliability and ruggedness against latch-up induced destruction, particularly in forming reliable source and body contact regions.
Innovation Solution
A method involving the formation of elevated source regions and recessed body regions through dopant implantation, followed by a sacrificial etch process to create defined contact surfaces, enhancing the device's reliability by correcting defects and providing redundancy against latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source and body contact regions are formed without elevated structures, then the device structure is simpler, but the reliability against latch-up induced destruction is insufficient
Solution Approach 1:
The contact region is segmented into multiple distinct components: elevated source regions protruding above the semiconductor body surface, recessed body regions etched below the surface, and dielectric layers filling the spaces between them. This segmentation creates physically separated contact paths that prevent latch-up propagation while maintaining electrical functionality.
Solution Approach 2:
The invention transitions from a planar contact structure to a three-dimensional structure by elevating source regions above the semiconductor body surface and recessing body regions below it. This vertical dimensionality addition creates spatial separation between source and body contacts, providing redundant current paths that enhance reliability against latch-up induced destruction.
2Reliability
If source regions are formed without precise definition, then the manufacturing process is simpler, but the probability of latch-up increases
Solution Approach 1:
A dielectric layer is deposited over the semiconductor body surface before forming the elevated source regions. This preliminary action creates a protective and defining layer that guides subsequent processing steps, ensuring precise source region formation and preventing defects that could lead to latch-up.
Solution Approach 2:
The dielectric layer acts as an intermediary material between the elevated source regions and the surrounding environment. It provides electrical isolation, defines the boundaries of source regions, and facilitates the formation of recessed body regions, thereby ensuring precise and reliable contact region definition.
3Manufacturing precision
If contact holes are formed before elevated source regions, then the process sequence is simpler, but the accuracy of contact alignment is reduced
Solution Approach 1:
The dielectric layer is deposited and processed before forming contact holes, establishing a reference structure that guides subsequent contact hole formation. This preliminary action ensures that contact holes are aligned with the intended source and body regions, improving contact alignment accuracy.
Solution Approach 2:
The dielectric layer serves as an intermediary reference structure during the contact hole formation process. By defining the spatial relationships between source and body regions beforehand, it enables precise alignment of contact holes with the elevated source regions and recessed body regions, even though this requires a more complex process sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves the reliability and ruggedness of power semiconductor devices by accurately defining source regions and reducing the probability of latch-up, ensuring reliable operation under stress conditions.
Implementation Method 1
implanting dopants of the first conductivity type into the semiconductor body
Implementation Method 2
removing portions of the semiconductor body that are uncovered by the recess mask layer by means of a first etch process
Implementation Method 3
removing portions of the dielectric layer uncovered by the contact hole mask layer by means of a second etch process
Data Source
AI summary
A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane.