Elevated Trace Package Substrate for Bond Line Confinement

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Solution Overview

Problem

Bond line thickness issues in semiconductor devices lead to reliability problems such as solder joint cracking and mold material delamination, which can affect chip level reliability, and existing solutions like taller copper bumps or increased solder paste add cost and complexity.

Innovation Solution

A multilevel package substrate with a conductive elevated trace layer featuring confinement features that laterally confine solder, adhesive, and die sides, enhancing bond line thickness and chip level reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If taller copper bump or conductive terminals are used on the bottom of the die, then bond line thickness reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvebond line thickness reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent introduces a vertical dimension by creating elevated trace features that extend upward from the substrate surface. These three-dimensional structures provide mechanical support and solder confinement without requiring taller copper bumps on the die itself, thus improving bond line reliability while avoiding the cost penalty of modified die structures

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The elevated trace features act as intermediary structures between the substrate and the die/solder joint. These features provide the necessary mechanical support and solder containment function without requiring changes to the die structure, serving as a cost-effective mediator that achieves the reliability improvement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If more solder paste is used, then bond line thickness reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvebond line thickness reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Instead of increasing solder paste quantity in the horizontal plane, the patent utilizes the vertical dimension through elevated trace features. These structures confine solder laterally and provide mechanical support, allowing adequate bond line thickness with normal solder paste amounts, thus improving reliability without increasing material cost

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If refined mold flowing processing is used, then bond line thickness reliability is improved, but device complexity increases

Engineering Contradiction:
Improvebond line thickness reliabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The elevated trace features are formed during substrate fabrication before die attachment and molding. This preliminary structuring provides built-in solder confinement and mechanical support, eliminating the need for complex refined mold flowing processing during assembly, thus improving reliability while simplifying the overall manufacturing process

Inventive Principle:
Principle #10Preliminary action

4Reliability

If confinement features are added to the substrate, then adhesion integrity is improved, but substrate complexity increases

Engineering Contradiction:
Improveadhesion integrityVSAvoidsubstrate complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The elevated trace features perform multiple functions simultaneously: they provide electrical connectivity as traces, provide mechanical support through their vertical structure, and provide solder/adhesive confinement through their lateral walls. This multi-functionality achieves improved adhesion integrity without proportionally increasing substrate complexity, as a single structural element delivers multiple benefits

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12381139B2Electronic device and multilevel package substrate with elevated trace features for solder and/or die confinement and method for fabricating the electronic device
Publication Date: 2025.08.05 TEXAS INSTRUMENTS INC
  • US12381139B2 patent drawing
  • US12381139B2 patent drawing
  • US12381139B2 patent drawing

AI summary

An electronic device with a multilevel package substrate having multiple levels including a first level having conductive leads and a final level having conductive landing areas along a side, as well as a die mounted to the multilevel package substrate and having conductive terminals electrically coupled to respective ones of the conductive leads, and a package structure that encloses the die and a portion of the multilevel package substrate, where the multilevel package substrate has a conductive elevated trace layer with a confinement feature that extends outward from the side of the final level along a third direction that is orthogonal to the first and second directions, the confinement feature having a sidewall configured to laterally confine one of a solder, an adhesive, a side of a passive component, and a side of the die.