Elliptical Via Wiring for 3D Semiconductor Memory Area Reduction
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Solution Overview
Problem
The increasing chip area in semiconductor memory devices due to the need for via wiring connections between different cell array layers limits packaging density and increases manufacturing costs.
Innovation Solution
A semiconductor memory device with a laminating structure where first and second wirings are formed in perpendicular layers, and via wiring connections are made with an elliptical cross-section orthogonal to the laminating direction, allowing for efficient sharing of word and bit lines across layers and reducing the chip area by optimizing the layout of via wiring connecting sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If via wiring connections are provided between different cell array layers, then wiring connectivity is achieved, but chip area increases
Solution Approach 1:
The patent transitions from planar via wiring connections to three-dimensional stacked memory architecture. Multiple cell array layers are stacked vertically with connection wirings extending in the thickness direction, enabling inter-layer connectivity without increasing chip area. This dimensional change allows via wiring to connect different layers through vertical stacking rather than lateral expansion.
Solution Approach 2:
The patent implements a nested structure where multiple cell array layers are stacked within a compact chip footprint. Connection wirings are embedded within the stacked structure, with lower-layer wirings positioned beneath upper-layer wirings. This nesting approach allows multiple wiring layers to coexist in a vertical arrangement, achieving complex connectivity without lateral expansion.
2Ease of manufacture
If wiring ends are provided in each cell array layer for via wiring connection, then inter-layer connectivity is achieved, but chip area increases
Solution Approach 1:
The patent moves wiring connections from the plane to the vertical dimension. Connection wirings extend in the thickness direction to connect cell array layers, eliminating the need for lateral wiring ends in each layer. This vertical connection approach achieves inter-layer connectivity without consuming additional chip area.
Solution Approach 2:
The patent merges the functions of multiple wiring layers into a compact stacked structure. Connection wirings from different layers are combined in the vertical direction, with lower-layer connection wirings positioned beneath upper-layer connection wirings. This merging reduces the total wiring area by utilizing the third dimension for routing.
3Quantity of substance
If cross-point structure with Schottky diode and resistance variation element is adopted, then package density increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements a three-dimensional stacked memory structure where multiple cell array layers are stacked vertically. This vertical stacking increases package density without requiring complex planar arrangements. The connection wirings extend in the thickness direction to connect stacked layers, simplifying the overall manufacturing process compared to complex planar cross-point structures.
Solution Approach 2:
The patent divides the memory structure into multiple discrete cell array layers that can be manufactured separately and then stacked. Each layer contains memory cells with standardized structures, reducing manufacturing complexity. The segmentation allows for modular manufacturing and assembly, making the high-density structure more manufacturable.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.