Elongated Bump Layout for High Density Semiconductor Packages
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Solution Overview
Problem
Conventional bump on pad layouts in semiconductor packaging struggle to achieve fine pitch due to fundamental layout constraints, resulting in low I/O count density and RC delay issues, especially with the use of circular copper bumps and mixed pattern wiring, which limits the reduction of pitch between terminals and increases thermal stress.
Innovation Solution
A semiconductor package design with elongated conductive bumps and a modified layout that increases I/O count density by aligning long axes of bumps in different directions, allowing for a fourfold increase in bump density and reducing the impact of CTE mismatch, while using a semi-additive or embedded pattern plating substrate to minimize RC delay and thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional circular copper bumps are used in bump on pad layouts, then manufacturing is simplified, but I/O count density is limited and pitch between terminals cannot be reduced further
Solution Approach 1:
The patent transitions from conventional circular bumps to elongated bumps with aspect ratios greater than 1, effectively utilizing dimensional change to increase I/O count density. The elongated shape allows bumps to be arranged in multiple orientations (0 degrees, 45 degrees, 90 degrees, 135 degrees), enabling fourfold increase in bump density within the same footprint area while maintaining manufacturability through standardized fabrication processes.
2Productivity
If pitch between terminals is reduced to increase I/O density, then more terminals fit in same area, but bridging shorts and non-uniform bump height occur
Solution Approach 1:
The patent segments the bump population into multiple groups oriented at different angles (0°, 45°, 90°, 135°), with each segment occupying a distinct spatial orientation. This segmentation prevents bridging between adjacent bumps by ensuring sufficient spacing in all directions, while the distributed orientation pattern maintains uniform stress distribution during reflow processing, eliminating non-uniform bump height issues.
3Ease of operation
If mixed pattern wiring is used in conventional layouts, then routing flexibility is maintained, but RC delay increases and thermal stress is exacerbated
Solution Approach 1:
The patent employs asymmetric elongated bump shapes with specific aspect ratios and orientations rather than symmetric circular bumps. This asymmetry, combined with the four-directional orientation pattern (0°, 45°, 90°, 135°), creates an optimized electrical field distribution that reduces RC delay by minimizing signal path interference. The asymmetric layout also improves thermal stress distribution by creating more uniform heat dissipation pathways across the substrate.
Data Source
AI summary
The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.