Elongated Bump Over Via in IC Package Substrate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flip-chip packaging technologies face challenges in reducing substrate unit cost and improving electrical integrity and performance due to increased complexity and density of bump arrays, which necessitate additional routing layers and vias, leading to higher manufacturing costs and potential performance issues.
Innovation Solution
The implementation of an integrated circuit package system that includes an elongated recess in a resist layer over a substrate, forming a via below the recess, and creating an elongated bump within this recess to enhance electrical connectivity without increasing the number of routing layers, using a conductive material to connect the bump pad over via to lower layer traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional routing layers and vias are added to support increased bump array density, then electrical connectivity is improved, but substrate unit cost increases drastically
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by forming vias through the substrate. This allows electrical connections to be established in the vertical dimension rather than requiring additional horizontal routing layers, thereby maintaining electrical connectivity while reducing substrate complexity and cost.
2Productivity
If bump array density is increased to support higher pin count, then IC performance is improved, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent segments the bump array into distinct regions with different pitch requirements. Peripheral bonds have a first pitch while inner bonds have a second pitch, allowing the manufacturing process to accommodate varying density requirements without requiring uniformly high precision across the entire array, thus enabling higher overall pin count while managing manufacturing complexity.
3Manufacturing precision
If peripheral I/O pads are redistributed into area array pads, then pitch is relaxed, but device complexity increases due to redistribution leads
Solution Approach 1:
The patent uses vertical vias to create three-dimensional routing paths that connect peripheral pads to area array pads without requiring complex planar redistribution leads. This vertical routing approach simplifies the overall device structure while achieving pad redistribution, reducing device complexity compared to traditional planar redistribution methods.
Data Source
AI summary
An integrated circuit package system includes a substrate, forming a resist layer having an elongated recess over the substrate, forming a via in the substrate below the elongated recess, and forming an elongated bump in the elongated recess over the via.