Elongated Contacts for Multi-Active Area ICs
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Solution Overview
Problem
Current photolithographic techniques for forming contacts and interconnects in integrated circuits face limitations due to spatial resolution issues, particularly when trying to connect multiple active areas or MOS gates, as existing equipment with higher resolution is expensive.
Innovation Solution
The method involves performing exactly two exposure operations for contact and interconnect patterns, using optional hard mask layers, and employing a damascene process to form elongated contacts and first-level interconnects that connect multiple active areas or MOS gates, allowing for direct connections without requiring high-resolution photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic equipment with smaller spatial resolution limit is used, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The contact formation process is segmented into two separate exposure operations: first forming contact holes through dielectric layers, then forming elongated contacts connecting multiple active areas. This segmentation allows each exposure step to have relaxed resolution requirements compared to forming all features in a single high-resolution step.
Solution Approach 2:
The invention transitions from planar contact structures to three-dimensional elongated contacts that extend vertically and horizontally to connect multiple active areas. This dimensional change allows contacts to bridge gaps that would be too small for conventional photolithography to resolve in a single layer.
2Manufacturing precision
If photolithographic equipment with smaller spatial resolution limit is used, then manufacturing precision is improved, but cost increases
Solution Approach 1:
By dividing the contact formation into two exposure operations with different pattern requirements, the invention enables use of lower-cost photolithographic equipment for each step, avoiding the need for expensive high-resolution equipment that would be required to form all features in a single exposure.
Solution Approach 2:
The first exposure operation preliminarily forms contact holes and initial contact structures, which then serve as foundations for the second exposure operation that completes the elongated contact formation. This preliminary action simplifies the requirements for the second exposure and reduces overall equipment cost requirements.
3Device complexity
If conventional photolithographic methods are used for forming contacts and interconnects, then process simplicity is maintained, but manufacturing precision deteriorates due to spatial resolution limits
Solution Approach 1:
The conventional single-exposure process is segmented into two sequential exposure operations, each with optimized pattern requirements. This segmentation maintains overall process simplicity while achieving superior spatial resolution for the elongated contact structures that connect multiple active areas.
Solution Approach 2:
The invention introduces vertical elongation of contacts to connect multiple active areas, adding a dimensional aspect that conventional planar photolithography cannot achieve. This dimensional change enables precise connection of separated active areas without requiring prohibitively high horizontal resolution.
Data Source
AI summary
An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.