Elongated Copper Pillar Bump for Flip Chip Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Circular copper pillar bumps in flip chip technology face limitations due to increased size, mechanical stress, and electrical current density, which hinder device miniaturization and reliability, particularly affecting low-k dielectric layers and leading to issues like delamination and electromigration.
Innovation Solution
The use of elongated bump structures with a conductive pillar and under-bump metallurgy layer, featuring a copper pillar with a specific geometry and dimensions, to reduce stress and enhance bonding reliability, allowing for tighter pitch and broader bonding windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circular copper pillar bumps are used for high-density flip chip interconnects, then connection density is improved, but pitch dimension is increased and device miniaturization is limited
Solution Approach 1:
The patent applies asymmetry by changing the bump geometry from circular to rectangular. The rectangular bump has different dimensions in length and width, with the length extending along the interconnect direction and width controlling the pitch. This asymmetric shape allows optimized spacing and alignment with metal trace lines, enabling tighter pitch dimensions while maintaining high connection density for device miniaturization
2Productivity
If circular copper pillar bumps are used, then connection density is improved, but mechanical stress increases causing dielectric layer delamination
Solution Approach 1:
The rectangular bump geometry distributes mechanical stress more evenly across the bonding interface compared to circular bumps. The elongated shape aligns with the stress distribution patterns in flip chip packaging, reducing stress concentration at the edges of the under-bump metallization layer and preventing dielectric layer delamination in low-k regions
Solution Approach 2:
The patent applies local quality by optimizing the bump shape to match the local stress distribution requirements. The rectangular geometry provides enhanced edge support at critical locations where stress concentration occurs, particularly protecting the low-k dielectric layers from delamination while maintaining overall connection density
3Productivity
If circular copper pillar bumps are used, then connection density is improved, but electrical current density increases causing electromigration
Solution Approach 1:
The rectangular bump shape optimizes the current distribution path by extending the conductive cross-section in the length direction while controlling the width. This asymmetric geometry reduces current density concentration at the bump-to-pad interface, mitigating electromigration effects and electrical stress while maintaining high connection density through optimized spacing
Data Source
AI summary
A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d1) measured along the long axis of the conductive pillar and a second dimension (d2) measured along the short axis of the conductive pillar. A ratio of L to d1 is greater than a ratio of W to d2.