Error-Locator Polynomial Early Exit for Low-Latency RS Decoding

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Solution Overview

Problem

Traditional Reed Solomon decoders perform 2*t iterations of the Berlekamp-Massey algorithm to determine error locator polynomials, leading to high latency even for FEC blocks with low error counts, which is inefficient and increases system latency.

Innovation Solution

Implementing an early exit mechanism based on the stability of the error locator polynomial determination, allowing the decoder to stop iterations when the estimated ELP is confirmed to be final, reducing the number of iterations to 2*v, where v is the actual number of errors, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If 2*t iterations of the Berlekamp-Massey algorithm are performed to determine error locator polynomials, then the decoder ensures complete error correction capability, but the system latency increases even for FEC blocks with low error counts

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsystem latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the number of iterations adaptive rather than fixed. The Berlekamp-Massey algorithm dynamically adjusts the iteration count based on the actual error pattern detected in the received data. When fewer errors are present, the algorithm converges earlier, allowing the system to exit the iteration loop before completing the full 2*t iterations, thus reducing latency while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements partial action by performing only the necessary number of iterations required to converge on the error locator polynomial, rather than always executing the full 2*t iterations. The algorithm performs partial iterations when the error count v is less than the maximum correctable errors t, executing exactly 2*v iterations which is sufficient for the actual error pattern but less than the maximum designed capacity.

Inventive Principle:
Principle #16Partial or excessive action

2Ease of manufacture

If the decoder performs all 2*t iterations regardless of actual error count, then the implementation is simple and deterministic, but the processing efficiency decreases for low error count scenarios

Engineering Contradiction:
Improveimplementation simplicityVSAvoidprocessing efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent employs feedback by using the discrepancy value calculated during each iteration to determine whether to continue or terminate the algorithm. The feedback mechanism monitors the convergence status of the error locator polynomial and provides control signals to exit the iteration loop early when convergence is achieved, thereby improving processing efficiency while maintaining implementation feasibility through structured control logic.

Inventive Principle:
Principle #23Feedback

3Loss of time

If early exit from iterations is implemented based on convergence detection, then processing time is reduced for low error counts, but the device complexity increases due to additional control logic

Engineering Contradiction:
Improveiteration processing timeVSAvoidcontrol logic complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies self-service by designing the Berlekamp-Massey algorithm to automatically detect its own convergence status through the discrepancy value calculation. The algorithm monitors its own execution state and self-determines when to terminate iterations based on the convergence criterion, eliminating the need for complex external control logic while achieving early exit functionality.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240204802A1Early exit error-locator polynomial determination
Publication Date: 2024.06.20 MICROCHIP TECHNOLOGY INC
  • US20240204802A1 patent drawing
  • US20240204802A1 patent drawing
  • US20240204802A1 patent drawing

AI summary

A method may include generating a status signal, the status signal to indicate a status of Error-Locator-Polynomial (ELP) determination by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit at least partially responsive to a value of the status signal.