eLRDIMM Multiplexing for High Bandwidth Memory Channels
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Solution Overview
Problem
Current memory channel designs, such as those using DDR5, face limitations in increasing memory channel bandwidth due to the multi-drop bus approach, which restricts operating frequency and data rate, despite efforts to expand memory capacity and reduce power consumption.
Innovation Solution
The implementation of an enhanced Load Reduced DIMM (eLRDIMM) that uses point-to-point data busses to connect DIMMs to the host, allowing for multiplexed data transfers between multiple ranks of memory chips over a single burst time window, effectively doubling the bandwidth by utilizing two separate 32-bit data busses and maintaining the frequency and speed of individual memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-drop bus approach is used to connect memory chips, then memory channel capacity can be increased, but operating frequency and data rate are restricted
Solution Approach 1:
The patent segments the memory channel into multiple point-to-point data busses (first 32-bit data bus and second 32-bit data bus) instead of using a shared multi-drop bus. Each data bus is dedicated to specific memory ranks, allowing simultaneous independent operations at high speeds while maintaining increased memory channel capacity through parallel data paths.
2Productivity
If memory channel bandwidth is increased, then data transfer rate improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic multiplexing where the same physical data bus infrastructure is dynamically allocated to serve different memory ranks at different times. During a single burst time window, data transfers are multiplexed between multiple ranks over the point-to-point busses, effectively doubling bandwidth utilization without proportionally increasing power consumption, as the same physical pathways are reused rather than requiring additional dedicated channels.
Data Source
AI summary
A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.