Enhanced Look-Up Table With Bank Segmentation For High-Throughput Signal Processing
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Solution Overview
Problem
Existing digital signal processing technologies face inefficiencies in manipulating data within look-up tables, particularly in image processing, due to limitations in command throughput, random access capabilities, and handling of redundant or non-unique addresses, which hinder rapid and flexible processing.
Innovation Solution
An enhanced look-up table integrated into a semiconductor chip that supports read-modify-write commands, random vectored access, and a programmable 'door-knock' feature to manage access delays, allowing for efficient processing of commands such as histogram manipulations and sliding window operations with a throughput of one command per clock pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a classic lookup table is used to replace runtime computation with simpler lookup operations, then processing speed is improved, but the device cannot efficiently handle random vectored access or simultaneous operations on multiple addresses
Solution Approach 1:
The lookup table is divided into multiple banks (e.g., 8 banks of 256 entries each) that can be independently accessed. This segmentation allows simultaneous operations on multiple addresses across different banks, enabling random vectored access while maintaining high processing speed through parallel operations.
Solution Approach 2:
The patent introduces a bank select dimension in addition to the traditional address dimension. By adding this control dimension, the system can independently access multiple banks simultaneously, transforming a single-dimension sequential access structure into a multi-dimension parallel access structure, thereby enabling random vectored access capabilities.
2Reliability
If multiple operations are performed sequentially on lookup table entries, then processing accuracy is maintained, but command throughput is reduced below one command per clock pulse
Solution Approach 1:
The patent implements a pipelined architecture where different stages of command processing occur simultaneously in different clock cycles. While one command is being executed in the execution stage, another command can be fetched in the fetch stage, ensuring continuous useful action and maintaining one command per clock pulse throughput without sacrificing processing accuracy through proper pipeline registration and timing control.
Solution Approach 2:
The system performs preliminary actions by pre-fetching commands and operands into buffer registers before execution is needed. This allows the main execution pipeline to operate continuously without waiting for data preparation, maintaining both accuracy through proper data validation and high throughput through overlapped operation stages.
3Adaptability or versatility
If redundant address operands are allowed in commands, then flexibility in programming is improved, but additional logic is required to detect and process identical addresses
Solution Approach 1:
The patent implements self-service by allowing redundant address operands to naturally point to the same physical location in the lookup table. The hardware automatically handles the redundancy by recognizing that multiple address operands can reference the same bank and entry, eliminating the need for complex duplicate detection logic while maintaining programming flexibility.
Solution Approach 2:
The patent merges the handling of redundant addresses by allowing multiple address operands to simultaneously reference the same physical storage location. The write-back logic combines updates to the same location, and the bank selection logic automatically handles conflicts, reducing the need for separate duplicate detection circuitry while preserving programming flexibility.
4Device complexity
If a simple register array is used for storage, then device complexity is minimized, but the ability to perform read-modify-write operations and histogram manipulations is limited
Solution Approach 1:
The patent implements a universal lookup table structure that can perform multiple functions including read-modify-write operations, histogram manipulations, and general data access. By incorporating programmable control logic that can interpret different command types and operate on the same basic register array structure, the system achieves multi-functionality without significantly increasing structural complexity, maintaining processing efficiency through unified hardware resources.
Data Source
AI summary
An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.