Electromigration Analysis Method for Integrated Circuit Layouts
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Solution Overview
Problem
The increasing current density in smaller metal interconnect layers of integrated circuits due to electromigration (EM) poses a significant reliability concern, as existing design tools are time-consuming and inefficient in simulating and verifying compliance with EM rules, especially for large and complex circuit layouts.
Innovation Solution
A method for analyzing EM in integrated circuits involves simulating circuit properties, comparing them to EM rules, and performing an EM rule relax procedure to decrease EM severity ratios, thereby avoiding negligible violations and reducing design overhead and layout size, using EDA tools and computer systems capable of high-speed calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional EM simulation tools are used to check compliance with EM rules for large and complex circuit layouts, then EM violations can be detected, but the analysis process becomes time-consuming and inefficient
Solution Approach 1:
The patent segments the EM analysis process into multiple passes: a first pass that performs comprehensive EM simulation and rule checking, and a second pass that performs targeted analysis only on layout portions that potentially violate EM rules. This segmentation reduces the overall analysis time by avoiding redundant simulations on compliant portions of the layout while maintaining detection of all EM violations.
2Reliability
If strict EM rules are applied to all metal segments, then EM reliability is ensured, but design overhead and layout size increase due to conservative design requirements
Solution Approach 1:
The patent applies local quality by differentiating EM rule application based on the specific characteristics of each metal segment. Instead of uniformly applying strict EM rules to all segments, the system identifies segments with potential EM violations and applies relaxed rules to segments that are already compliant. This allows the design to maintain EM reliability for critical segments while reducing design overhead and layout size for non-critical segments.
Data Source
AI summary
Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.