Electromigration Analysis in Integrated Circuit Metal Segments
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Solution Overview
Problem
The increasing current density in smaller metal interconnect layers of integrated circuits due to electromigration (EM) poses a significant reliability concern, as existing design tools are inefficient in simulating and addressing EM violations, especially in large and complex circuit layouts, leading to potential shortening of circuit lifetime.
Innovation Solution
A method is introduced to analyze and mitigate EM in integrated circuits by simulating circuit properties, comparing them to EM rules, and performing an EM rule relax procedure to decrease EM severity ratios, thereby avoiding negligible violations and reducing design overhead and layout size. This involves selecting metal segments and vias based on current simulation results, relaxing EM rules when specific conditions are met, such as multiple vias with the same current direction, to ensure compliance without over-design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EM simulation is performed on large and complex IC layouts, then EM compliance can be determined, but the process becomes time consuming
Solution Approach 1:
The patent segments the IC layout into multiple tiles, where each tile is independently processed for EM simulation. This divides the large-scale simulation problem into smaller, parallelizable sub-problems, reducing overall simulation time while maintaining accuracy for determining EM compliance.
Solution Approach 2:
The patent performs EM simulation on selected tiles rather than the entire layout, and applies EM rules selectively to metal segments within those tiles. This partial action approach determines EM compliance efficiently by focusing computational resources on critical regions rather than performing exhaustive full-layout simulation.
2Reliability
If EM rules are applied strictly to all metal segments, then reliability is improved, but design overhead and layout size increase
Solution Approach 1:
The patent applies EM rules locally to specific metal segments within selected tiles rather than uniformly to the entire layout. By identifying and processing only the metal segments that require EM rule checking, the patent reduces design overhead and layout complexity while maintaining reliability improvements in critical areas.
Solution Approach 2:
The patent applies EM rules partially to only those metal segments in selected tiles that meet specific criteria, rather than applying rules to all metal segments in the layout. This selective application reduces design overhead and avoids unnecessary modifications while still improving circuit lifetime where it matters most.
Data Source
AI summary
Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.