Electromigration-Aware IC Design Protected Zones
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Solution Overview
Problem
Newer integrated circuit (IC) technologies face increasing issues with electromigration (EM) failures due to higher operating frequencies and smaller chip sizes, leading to voids and shorts in interconnect networks, which are not effectively addressed by current design methods that consider EM verification late in the process, resulting in significant redesign time.
Innovation Solution
Electromigration-aware IC design methods and systems that acquire EM-relevant information early in the design process to define protected zones around library elements, preventing placement within these zones and optimizing library element placement relative to power rails to minimize EM failures, and optionally apply this approach to clock distribution networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EM verification is performed late in the design process, then the design process follows traditional sequencing, but EM failures are not effectively addressed requiring significant redesign time
Solution Approach 1:
The patent applies preliminary action by performing EM-aware library element placement early in the design process, before final layout completion. Protected zones are defined around library elements during the placement phase based on EM-relevant information, preventing EM failures before they occur rather than detecting and correcting them later through verification and redesign
2Reliability
If protected zones are defined around library elements, then EM fails are prevented in the power delivery network, but placement options are restricted
Solution Approach 1:
The patent applies local quality by creating protected zones around specific library elements that have high EM risk, rather than applying uniform restrictions across the entire design. The protected zone radius for each library element is calculated based on its specific EM-relevant information, allowing flexible placement in areas not covered by protected zones while maintaining reliability where needed
3Productivity
If EM-relevant information is acquired early in the design process, then EM-aware placement can be performed timely, but additional processing steps are required
Solution Approach 1:
The patent merges EM-aware placement with the standard library element placement process. The placement tool simultaneously performs conventional placement optimization and EM-aware protected zone enforcement in a single integrated process, rather than requiring separate sequential steps for placement and EM verification
Solution Approach 2:
The system automatically acquires EM-relevant information from technology files, design specifications, and library files without requiring manual designer input. The placement tool self-determines protected zone radii based on the library element characteristics and power delivery network parameters, eliminating the need for manual EM analysis by the designer
Data Source
AI summary
Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.