Electromigration-Aware Layout Generation for Chip Reliability
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Solution Overview
Problem
As feature sizes in chips decrease, increasing current densities through wires lead to electromigration issues such as hillock or void formation, reducing the mean time to failure (MTTF) and potentially causing short or open circuits.
Innovation Solution
An EM-aware layout generation system is implemented, which includes tools for determining electromigration susceptibility (EMS) of cells and generating layout constraints to manage current densities, ensuring reliable wire performance by optimizing placement and routing based on maximum loading capacitance and geometric constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire size is reduced to continue scaling, then chip functionality and integration density improve, but current density increases causing electromigration and reducing MTTF
Solution Approach 1:
The patent applies local quality by determining electromigration susceptibility (EMS) for different regions of the chip layout and generating cell-specific layout constraints. Each cell receives customized placement and routing constraints based on its local EMS characteristics, allowing the design to accommodate varying current density risks in different areas while maintaining overall scaling benefits.
Solution Approach 2:
The patent changes physical parameters by adjusting wire width, placement distance, and routing geometry based on calculated EMS values. The system modifies layout parameters dynamically - increasing wire width or spacing in high-EMS regions while maintaining tighter constraints in low-EMS regions, thus resolving the contradiction between scaling and reliability.
2Reliability
If EM-aware layout constraints are applied to each cell, then wire reliability improves, but design complexity and computation time increase
Solution Approach 1:
The patent applies preliminary action by calculating EMS values and generating layout constraints during the cell characterization phase, before actual placement and routing. This advance preparation allows the placement and routing tools to directly apply pre-computed constraints without real-time computation, significantly reducing design complexity and computation time during the main design flow.
Solution Approach 2:
The system implements self-service by having each cell automatically determine its own EMS characteristics and receive customized constraints based on its specific geometry and electrical properties. This cell-level autonomy eliminates the need for complex global optimization algorithms, as each cell independently manages its own electromigration risks through pre-generated constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively extends the MTTF of wires by managing current densities and preventing electromigration-induced failures, ensuring reliable chip performance and reducing the risk of timing and performance degradation.
Implementation Method 1
A life span of a wire is subject to electromigration, which is a material transport caused by transfer of momentum between conducting electrons and metal ions
Data Source
AI summary
In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.