Electromigration-Aware Power Rail Placement
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Solution Overview
Problem
As feature sizes in chips decrease and functionalities increase, the current densities through wires rise, leading to increased electromigration, which can cause hillocks or voids, resulting in short circuits or open circuits and a decrease in mean time to failure (MTTF).
Innovation Solution
An EM-aware placement method is implemented during the design flow of integrated circuit chips, where the current through each power rail segment is analyzed, and cells with overlapping switching windows are grouped to optimize placement, constraining EM usages to limit electromigration susceptibility, thereby reducing the risk of wire failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wire size is reduced to increase functionality, then chip functionality increases, but current density increases causing electromigration
Solution Approach 1:
The patent applies local quality by differentiating power rail segments based on their electromigration susceptibility and current characteristics. Each segment is evaluated individually with its own EM usage metrics, allowing targeted placement optimization for high-risk segments while maintaining standard placement elsewhere, thus resolving the contradiction between functionality and reliability.
Solution Approach 2:
The patent performs preliminary action by calculating electromigration usage for each power rail segment before final placement is determined. By pre-evaluating EM susceptibility and constraining placement decisions based on these pre-calculated metrics, the system prevents electromigration issues before they occur, maintaining both high functionality and wire reliability.
2Productivity
If current density increases due to scaling, then chip functionality increases, but electromigration susceptibility increases
Solution Approach 1:
The patent implements feedback by continuously monitoring and calculating EM usage for each power rail segment based on cell placement and current characteristics. This feedback loop allows the placement optimization to adjust cell positions to reduce EM susceptibility while maintaining required functionality, directly addressing the contradiction between productivity and harmful factors.
Solution Approach 2:
The patent applies parameter changes by modifying placement parameters (cell positions) based on EM usage calculations. When high current density is detected in a region, the system changes placement parameters to redistribute cells and reduce EM susceptibility, thus resolving the contradiction between maintaining chip functionality and reducing electromigration effects.
3Reliability
If placement is optimized for EM usage, then wire reliability increases, but design complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the power distribution network into discrete power rail segments and evaluating EM usage for each segment independently. This segmentation allows the complex placement optimization problem to be broken down into manageable per-segment evaluations, reducing overall design complexity while maintaining wire reliability.
Solution Approach 2:
The patent implements self-service by having the placement optimization system automatically calculate EM usage metrics and adjust placements based on these calculations without requiring manual intervention. This automation reduces design complexity by eliminating manual EM analysis while maintaining high wire reliability through systematic optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes the placement of power rail segments, reducing electromigration-induced failures by accurately managing current densities and extending the mean time to failure of wire connections.
Implementation Method 1
A life span of a wire is subject to electromigration, which is a material transport caused by transfer of momentum between conducting electrons and metal ions
Data Source
AI summary
In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.