EM Resistant IC Feed Line Parallel Sub-Trace Design
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Solution Overview
Problem
Conventional flip chip solder bump structures suffer from current non-uniformity across the cross-sectional area, leading to premature electromigration-induced failures due to high current density limitations, which are exacerbated by the low current handling capacity of solder compared to metals like copper and aluminum.
Innovation Solution
The implementation of feed line structures divided into electrically parallel sub-traces with varying lengths and widths to distribute current uniformly across the bonding feature, ensuring each sub-trace carries substantially equal current density, thereby reducing electromigration-induced voiding and failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single feed line trace is used to supply current to a solder bump, then the structure is simple and easy to manufacture, but the current distribution becomes highly non-uniform leading to premature electromigration failures
Solution Approach 1:
The single feed line trace is divided into multiple parallel sub-traces (at least three) that are distributed around the periphery of the solder bump. Each sub-trace carries a portion of the total current, distributing the current more uniformly across the solder bump's cross-sectional area. This segmentation reduces current crowding at any single location and prevents premature electromigration-induced voiding, thereby improving reliability without significantly complicating the manufacturing process.
2Reliability
If the feed line current is concentrated in a small region adjacent to the UBM, then the connection is direct and efficient, but the current density exceeds the EM limit causing voiding and failure
Solution Approach 1:
The feed line structure is designed with sub-traces of varying widths and lengths tailored to their specific locations. Sub-traces closer to the UBM region (which has lower current carrying capacity) are made narrower or longer to carry less current, while sub-traces in regions with higher current capacity are made wider or shorter. This local customization of sub-trace geometry ensures that current density is evenly distributed across the entire solder bump cross-section, preventing EM-induced voiding and extending solder bump lifespan.
3Power
If solder bumps are used to provide connections, then the flip chip device can be joined effectively, but the current handling capability is limited to around 104 A/cm2 which is 100 times lower than copper or aluminum
Solution Approach 1:
Instead of attempting to increase the current carrying capacity of individual solder bumps (which is limited by material properties), the invention distributes the current load across multiple spatial dimensions by arranging multiple sub-traces around the periphery of the solder bump. This dimensional distribution approach allows the system to handle higher total current (e.g., 10 amps or more) by leveraging the collective capacity of multiple solder bumps or regions, effectively bypassing the low current density limit of individual solder joints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the current carrying capacity of bonding features like solder bumps by achieving more uniform current distribution, reducing electromigration-induced failures and extending the lifespan of solder bumps by 200-300% to over 1000% compared to conventional designs.
Implementation Method 1
EM is a known phenomenon in which atoms of a metal feature are displaced due to the electrical current passing through the metal feature.
Data Source
AI summary
An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.