Embedded 2D Crystal Transistors for Low-Temperature IC Integration
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Solution Overview
Problem
Temperature limitations and complex semiconductor processes hinder the integration of small-scale semiconductor structures in integrated circuits, leading to increased manufacturing time and costs.
Innovation Solution
The integration of thin film crystal transistors with embedded layers of less than 10 nm thickness, comprising two-dimensional crystalline layers with varying metal and chalcogen compositions, allows for reduced leakage current and contact resistance, enabling increased transistor density and efficiency through phase conversion techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor processes are used to form small-scale structures, then manufacturing complexity increases, but integration of required structures is impeded due to temperature limitations
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to thin-film crystal materials (such as transition metal dichalcogenides), which enable small-scale structure formation at lower temperatures compatible with back-end-of-line processes, thereby resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The patent employs composite material structures including thin-film crystal layers integrated with existing semiconductor devices and wiring layers, allowing small-scale transistor formation without requiring complete process redesign, thus reducing overall process complexity while achieving high precision
2Reliability
If conventional semiconductor processes are used, then manufacturing time increases, but temperature limitations prevent integration of required structures
Solution Approach 1:
The patent performs thin-film crystal formation and transistor integration during the back-end-of-line process stage, rather than requiring separate preliminary processing steps, which reduces total manufacturing time while ensuring reliable structure integration through low-temperature compatible processes
3Productivity
If transistor size is reduced to increase density, then leakage current increases, but conventional processes cannot achieve required precision
Solution Approach 1:
The patent changes the material parameters of the transistor channel to thin-film crystal materials with superior electrical characteristics that maintain low leakage current even at reduced dimensions, enabling high transistor density without the energy loss associated with conventional scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density, reduces power losses, and minimizes contact resistance, thereby improving the efficiency and package density of integrated circuits while being compatible with back-end-of-line processes.
Implementation Method 1
comprising two-dimensional crystalline layers with varying metal and chalcogen compositions, allows for reduced leakage current and contact resistance, enabling increased transistor density and efficiency through phase conversion techniques
Data Source
AI summary
An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.