Embedded 3D IC Substrate Layout for Smaller Footprint Integration
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Solution Overview
Problem
The electronics industry faces constraints in reducing the size of integrated circuit (IC) modules and circuit boards due to the two-dimensional footprint of IC dies, which limits the integration of increased functionality and performance.
Innovation Solution
Three-dimensional (3-D) integrated circuit structures are developed using die and/or wafer bonding technologies combined with embedded die packaging, allowing for electrical connection pad placement on both top and bottom surfaces, enabling high integration, miniaturization, and flexible circuit partitioning, and resulting in low-profile IC structures that leverage economies of scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2-D planar IC die structure is used, then manufacturing process is simple and well-established, but the footprint area is large and functionality is limited
Solution Approach 1:
The patent transitions from conventional 2-D planar IC die structure to a 3-D embedded die structure where the IC die is embedded within a laminate substrate at an angle (e.g., 45 degrees) rather than being flush-mounted. This dimensional change allows the IC die to occupy three-dimensional space within the substrate, effectively reducing the projected footprint area while maintaining manufacturing feasibility through modified lamination and drilling processes.
2Adaptability or versatility
If more transistors are added to increase functionality, then electronic performance improves, but the 2-D footprint increases
Solution Approach 1:
By embedding the IC die within the laminate substrate at an angle and utilizing vertical space within the substrate thickness, the patent enables higher transistor density and functionality without proportionally increasing the horizontal footprint. The 3-D configuration allows multiple IC dies to be stacked or arranged in vertical layers, effectively packing more electronic functionality into a smaller planar area.
Solution Approach 2:
The patent embeds the IC die within the laminate substrate structure, nesting the active electronic component inside the passive substrate material. This nesting approach allows the IC die to be surrounded by additional functional layers, passive components, and routing structures within the same vertical space, maximizing the utilization of available volume and enabling higher integration density.
3Area of stationary object
If 3-D embedded die structure is used, then footprint is reduced and integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the manufacturing process into distinct segments: (1) forming the laminate substrate with embedded passive components and routing layers, (2) embedding the IC die at a specific angle within the substrate, (3) drilling through-holes to expose contact pads, and (4) forming conductive paths to connect to external terminals. This segmentation of the manufacturing process makes the complex 3-D embedded structure more manageable and manufacturable by breaking it down into sequential, specialized steps.
Data Source
AI summary
Three-dimensional (3-D) integrated circuit (IC) structures that are less constrained by the 2-D footprint of a conventional IC die. The novel 3-D IC structures combine 3-D ICs fabricated using various die and/or wafer bonding technologies with embedded die packaging technology. Embodiments include a 3-D IC structure including one or more 3-D IC dies embedded within a stack of one or more planar lamination layers. Combining one or more 3-D ICs with embedded die packaging technology results in a high degree of integration and miniaturization by taking advantage of electrical connection pad placement on both top and bottom surfaces of the 3-D ICs, enables better integration of active components as well as passive components, enables flexible partitioning of circuits and systems for 3-D integration, and enables low-profile 3-D IC structures that take advantage of economies of scale.