Embedded Antenna Semiconductor Package for EMI Shielding and Warpage
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Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and electromagnetic interference (EMI) shielding, particularly in high-frequency and multi-band RF products, where spatial limitations and warpage issues hinder the integration of complex electronic components.
Innovation Solution
Integration of an antenna substrate within the semiconductor package, utilizing a through via to provide a vertical electrical connection path and shield electromagnetic waves, while allowing for compact and thin design, and independent encapsulation of passive components to prevent defects and foreign material issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an antenna substrate is integrated within the semiconductor package, then the package size and thickness are reduced, but electromagnetic interference shielding becomes more difficult
Solution Approach 1:
The antenna substrate is nested within the semiconductor package structure, with the antenna pattern integrated into the package substrate layers. This nesting approach allows the antenna to be contained within the package volume without increasing external dimensions, while the package substrate itself serves as part of the EMI shielding structure through its layered construction with ground patterns and via holes.
Solution Approach 2:
The package substrate acts as an intermediary structure between the antenna pattern and the external environment. The substrate's layered construction with ground patterns, via holes filled with conductive material, and multiple copper layers creates an EMI shielding barrier that protects external devices from electromagnetic interference while allowing the antenna to function internally.
2Volume of moving object
If components are closely integrated in a small package, then space is saved, but process warpage increases
Solution Approach 1:
The package substrate incorporates copper layers with controlled thickness parameters (first copper layer: 1-3 μm, second copper layer: 3-5 μm) and uses via holes with specific dimensions (diameter: 3-7 μm, depth: 50-150 μm) to adjust the mechanical and thermal properties of the structure. These parameter optimizations help balance the integration density with warpage control by tuning the substrate's stiffness and thermal expansion characteristics.
3Adaptability or versatility
If high-frequency RF products use wider bandwidth and multi-bands, then performance improves, but spatial limitations and interference issues worsen
Solution Approach 1:
The antenna design transitions from planar two-dimensional patterns to three-dimensional structures utilizing multiple layers of the package substrate. The antenna pattern is formed across different substrate layers with vertical connectivity through via holes, creating a 3D antenna system that achieves multi-band and wideband performance within a compact footprint by exploiting the third dimension (vertical stacking) rather than requiring larger horizontal area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of smaller, thinner semiconductor packages that effectively block EMI and address warpage control, facilitating the integration of complex components and improving manufacturing yield.
Implementation Method 1
provides a vertical electrical connection path using a through via penetrating portions of the semiconductor package and the antenna substrate
Implementation Method 2
enables process warpage control, while effectively blocking electromagnetic interference (EMI)
Data Source
AI summary
A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate.