Embedded Arithmetic Blocks for Smaller Structured ASICs
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Solution Overview
Problem
Structured application-specific integrated circuits (ASICs) face increased die area and cost when adding FPGA-style digital signal processing (DSP) blocks, which are not utilized in applications that do not require high precision, as these blocks occupy a larger proportion of the die area compared to FPGAs.
Innovation Solution
Embedding arithmetic blocks that emulate the functions of DSP blocks using a combination of ASIC components and structured logic, allowing for smaller footprint and reduced design and verification efforts, with the option to customize and assemble different modes as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA-style DSP blocks are added to structured ASIC, then arithmetic processing capability is improved, but die area and cost increase significantly
Solution Approach 1:
The patent segments the monolithic DSP block into multiple smaller arithmetic components (multipliers, adders, accumulators) that can be independently configured and interconnected. This allows the system to provide arithmetic processing capability through distributed components rather than a single large block, reducing the concentration of die area usage while maintaining overall processing capability.
Solution Approach 2:
The patent implements dynamic configurability where arithmetic components can be programmatically configured at runtime to perform different operations (multiplication, addition, accumulation, logical operations). This dynamic nature allows the same physical components to serve multiple arithmetic functions, improving adaptability without proportionally increasing die area.
2Adaptability or versatility
If FPGA-style DSP blocks are added to structured ASIC, then arithmetic processing capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent creates universal arithmetic components that can perform multiple functions (multiplication, addition, accumulation, logical operations) through programmable configuration. This multi-functionality allows a single set of components to replace what would traditionally require multiple dedicated blocks, reducing overall complexity and manufacturing cost while maintaining arithmetic processing capability.
Solution Approach 2:
The patent utilizes programmable parameters to change the behavior of arithmetic components at runtime. By modifying configuration parameters rather than hardware structure, the system achieves adaptability without increasing physical complexity, thereby controlling manufacturing costs while providing versatile arithmetic processing.
3Area of stationary object
If embedded arithmetic blocks are used, then die area is reduced, but design and verification complexity increases
Solution Approach 1:
The patent employs standardized, pre-verified arithmetic component designs that can be copied and reused throughout the system. Rather than designing unique arithmetic blocks from scratch, the invention uses replicated instances of proven components (multipliers, adders, accumulators), which reduces design complexity while achieving compact die area utilization.
Solution Approach 2:
The patent implements self-configuration capabilities where arithmetic components can be automatically configured through programmable interfaces. This self-service approach reduces the manual design and verification burden by allowing automated configuration tools to set up component behavior, thereby reducing design complexity while maintaining compact embedded block structures.
Data Source
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AI summary
An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.