Embedded Backside PCRAM Structure for Dense Memory Cell Alignment
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Solution Overview
Problem
The challenge in forming effective memory cells in integrated circuits, particularly in memory arrays, arises from the difficulty in reducing feature sizes while ensuring proper formation and alignment of components, especially in phase change random access memory (PCRAM) cells.
Innovation Solution
The integration of a gate all around (GAA) transistor with a phase change memory element is formed on the backside of a wafer after bonding, allowing the phase change memory element to be positioned below the transistor, utilizing double-patterning or multi-patterning photolithography processes to achieve precise alignment and reduced area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to increase computing power density, then more transistors and memory cells can be included in a given area, but the difficulty in ensuring proper formation and alignment of components increases
Solution Approach 1:
The patent positions the phase change memory element in a different spatial dimension (below the transistor in the substrate) rather than arranging it in the same plane. This vertical stacking approach allows both components to occupy the same footprint area while maintaining proper formation and alignment, thereby increasing computing power density without compromising manufacturing precision at reduced feature sizes
2Productivity
If the area footprint of memory cells is reduced to increase memory array density, then more memory cells can be included in a given area, but the difficulty in forming effective memory cells at smaller technology nodes increases
Solution Approach 1:
The phase change memory element is formed in a trench structure below the transistor, utilizing the vertical dimension to reduce the horizontal footprint. This allows the memory cell to occupy minimal area while maintaining effective formation at smaller technology nodes, as the critical alignment occurs vertically rather than horizontally
Solution Approach 2:
The phase change memory element is nested within a trench structure that is positioned below the transistor. This nested arrangement allows the memory element to be contained within the transistor's footprint area, achieving high density while maintaining proper formation effectiveness at reduced feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures that the area footprint of each memory cell is approximately equal to the transistor, providing efficient use of space and enabling the formation of a large array of PCRAM cells with minimal additional area, thus overcoming the challenges of reducing feature sizes in memory arrays.
Implementation Method 1
a phase change memory element electrically coupled to the transistor... by switching between crystalline and amorphous states
Implementation Method 2
a second chip bonded to the first chip... utilizing a wafer bonding process to facilitate the formation of these cells
Data Source
AI summary
An integrated circuit includes a first chip bonded to a second chip. The first chip includes an array of memory cells. Each memory cell includes a transistor and phase change memory element. The transistor is between the phase change memory element and the second chip.