Embedded Boot Verification for Multi-Flash Memory Controllers
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Solution Overview
Problem
Existing embedded electronic devices require multiple GPIO pins to configure different work modes for various types of external flash memories, occupying interface pins and complicating the boot process.
Innovation Solution
Implement a memory-mapped I/O (MMIO) architecture to verify the safety and correctness of external memory devices without using additional GPIO pins, utilizing multiple memory controllers to determine the correct correspondence between memory devices and controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple GPIO pins are used to configure different work modes for various types of external flash memories, then the embedded electronic device can support multiple memory types, but the interface pins are occupied and the boot process becomes complicated
Solution Approach 1:
The patent implements a universal memory access interface that can work with different types of external flash memories (NAND, NOR, eMMC, etc.) without requiring different GPIO configurations. The memory access module uses a unified protocol and data processing path that adapts to different memory types through automatic detection and configuration, eliminating the need for multiple specialized interfaces and reducing boot process complexity.
Solution Approach 2:
The system performs self-detection and self-configuration of the external memory device during the boot process. The processor automatically detects the memory type through the unified interface, configures the appropriate parameters, and initiates the verification process without requiring manual GPIO configuration or complex external setup, thereby simplifying the overall boot procedure.
2Adaptability or versatility
If multiple GPIO pins are used to configure different work modes for various types of external flash memories, then the embedded electronic device can support multiple memory types, but interface pins are occupied
Solution Approach 1:
The patent employs a single universal memory access interface that can communicate with multiple types of external flash memories using different protocols. This interface integrates the functionality of multiple specialized interfaces into one, allowing the same physical pins to serve multiple purposes through software configuration rather than requiring dedicated pins for each memory type.
Solution Approach 2:
The patent merges the functions of multiple specialized memory interfaces into a single unified memory access module. This consolidation combines the capabilities of NAND flash interfaces, NOR flash interfaces, and eMMC interfaces into one integrated component that uses a common set of GPIO pins, thereby reducing the total number of pins required while maintaining support for all memory types.
3Reliability
If traditional verification methods are used for external memory devices, then the safety can be verified, but additional GPIO pins are required and the process becomes more complex
Solution Approach 1:
The patent introduces a verification data structure and unified access protocol as intermediaries between the processor and external memory devices. This intermediary layer provides a standardized method for verifying memory safety that works across different memory types without requiring memory-specific verification routines or additional control pins, thereby maintaining reliability while reducing complexity.
Solution Approach 2:
The system changes the verification approach from hardware-configurable methods to software-based parameter verification. By using configurable verification parameters and data structures that can be adjusted through software, the system maintains flexible and thorough safety verification without requiring additional physical pins or complex hardware configuration, allowing verification to be performed through standard interface operations.
Data Source
AI summary
An embedded electronic device and a boot method are provided. A processor of the embedded electronic device is configured to execute following steps based on a first boot procedure: verifying whether a second memory device safely corresponds to a first memory controller; in response to that the second memory device safely corresponds to the first memory controller, deciphering and verifying stored data of the second memory device through the first memory controller; and in response to that the second memory device does not safely correspond to the first memory controller, verifying whether the second memory device safely corresponds to a second memory controller.


