Embedded Bridge Die Package Substrate for Fine-Pitch Interconnects
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Solution Overview
Problem
Current interconnect technologies in microelectronic packaging face challenges such as low vertical and horizontal interconnect density, high power consumption, increased cost, and manufacturing limitations, particularly in 2.5D organic package architectures, where bridge dies with through-silicon vias (TSVs) are difficult to align and assemble, and organic materials restrict fine pitch interconnections due to thermal expansion and shrinkage issues.
Innovation Solution
A microelectronic assembly with a package substrate that includes a first IC die embedded within and a second IC die conductively coupled to the substrate via vias in the substrate, with diameters less than 60 micrometers, utilizing a plurality of layers of conductive traces in an organic dielectric material, and employing solder bonding and underfill materials to enhance thermal and mechanical stability, allowing for direct coupling between compute dies and the package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional solder-based packaging with organic materials is used, then ease of manufacture is maintained, but interconnect density is low and power consumption is high
Solution Approach 1:
The package substrate is divided into multiple layers (first organic dielectric layer, second organic dielectric layer, copper foil layers) with conductive vias penetrating through specific layers. This segmentation allows for higher interconnect density while maintaining manufacturability through standardized layer-by-layer construction processes.
Solution Approach 2:
The invention transitions from traditional 2D surface mounting to a 3D embedded architecture where IC dies are positioned within recesses in the substrate and connected through vertical vias. This dimensional change enables significantly higher interconnect density by utilizing vertical space and multiple routing layers.
2Quantity of substance
If bridge dies with through-silicon vias are used in 2.5D organic package architecture, then interconnect density is improved, but alignment and assembly difficulty increases
Solution Approach 1:
Conductive vias are formed and prepared in the package substrate before the IC die is positioned and attached. Bond pads are pre-formed on the die and in the substrate, ensuring alignment features are ready in advance. This preliminary preparation simplifies the assembly process and reduces alignment difficulties during final die attachment.
Solution Approach 2:
The package substrate acts as an intermediary structure with pre-formed conductive vias and bond pads that facilitate alignment between the IC die and the underlying circuit board. The substrate's recess structure and pre-positioned electrical features serve as alignment references, reducing the precision requirements for direct die-to-board alignment.
3Manufacturing precision
If organic materials are used in package substrate, then ease of manufacture is maintained, but fine pitch interconnections are restricted due to thermal expansion and shrinkage
Solution Approach 1:
The package substrate uses a composite structure combining organic dielectric materials with copper foil layers and conductive via structures. This composite approach leverages the ease of manufacture of organic materials while the copper and via structures provide dimensional stability and support for fine pitch interconnections, compensating for organic material thermal expansion and shrinkage.
Solution Approach 2:
The invention changes the physical parameters of the package substrate by creating recesses with specific depth and dimension ratios, and by controlling via diameter and spacing. These parameter changes enable fine pitch interconnections by providing mechanical support and reducing the impact of organic material thermal expansion and shrinkage on connection precision.
4Quantity of substance
If vias with diameters less than 60 micrometers are used, then interconnect density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The via fabrication process is segmented into discrete steps: forming via holes through the organic dielectric layer, applying conductive material lining, and filling with conductive paste. This segmentation allows each step to be optimized independently, achieving precise sub-60 micrometer via dimensions through controlled processing rather than requiring single-step high-precision manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher interconnect density, reduced power consumption, and improved manufacturing yield by allowing direct coupling between compute dies and the package substrate, overcoming the limitations of traditional solder-based packaging and organic material constraints.
Implementation Method 1
The IC die is coupled to the bond pads by solder
Implementation Method 2
employing solder bonding and underfill materials to enhance thermal and mechanical stability
Implementation Method 3
a second IC die coupled to the package substrate and conductively coupled to the first IC die by conductive vias in the package substrate
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.