Embedded Bridge Package Architecture for Multi-Substrate Compute Integration

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Solution Overview

Problem

Existing microelectronics packaging technologies face challenges in efficiently connecting and integrating multiple computational components across different substrates, leading to complications in computation and protection requirements.

Innovation Solution

The proposed solution involves a package architecture with an embedded bridge, where a first layer includes a compute device and device stacks, and a second layer with bridges electrically connects the compute device to multiple device stacks, enabling efficient computation and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If connections are formed between substrates to increase computation, then computational capability is improved, but packaging complexity and protection requirements increase

Engineering Contradiction:
Improvecomputational capabilityVSAvoidpackaging complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The packaging structure is divided into multiple layers (first layer with compute device, second layer with bridges, third layer with device stacks) that can be independently manufactured and then assembled. This segmentation allows each layer to be optimized separately while reducing overall packaging complexity during integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Redistribution layers are introduced as intermediary structures between the compute device, bridges, and device stacks. These redistribution layers simplify the connection interface by redistributing signal paths, reducing the complexity of direct multi-substrate connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple computational components are integrated on multiple substrates, then computation is enhanced, but thermal and physical protection requirements increase

Engineering Contradiction:
Improvecomputation enhancementVSAvoidthermal and physical protection requirements
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from planar substrate connections to a three-dimensional stacked architecture with vertical interconnections. This dimensional change allows better thermal management by separating heat-generating compute devices from heat-sensitive memory stacks vertically, while maintaining compact integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Dielectric layers and encapsulation structures are introduced as intermediary protective elements between computational components. These intermediaries provide thermal isolation, mechanical protection, and electrical insulation, addressing protection requirements without compromising computational integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If substrates are connected to provide increased computation, then processing power is improved, but manufacturing complications increase

Engineering Contradiction:
Improveprocessing powerVSAvoidmanufacturing complications
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The manufacturing process is segmented into separate steps for fabricating the compute device layer, bridge layer, and device stack layer independently using standard semiconductor processes. This allows each layer to be manufactured using existing fabrication capabilities, reducing overall manufacturing complications.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Redistribution layers and connection structures are prepared in advance on each layer before final assembly. This preliminary action ensures that alignment and connection interfaces are pre-configured, simplifying the final integration process and reducing manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250201690A1System and methods for an embedded bridging package architecture
Publication Date: 2025.06.19 SAMSUNG ELECTRONICS CO LTD
  • US20250201690A1 patent drawing
  • US20250201690A1 patent drawing
  • US20250201690A1 patent drawing

AI summary

Disclosed herein are methods, systems and devices including a first layer with a first compute device, a first device stack, and a second device stack between the first device stack and the first compute device. A second layer may be mounted on top of the first layer. The second layer may include a first bridge electrically connecting the first compute device to the first device stack and a second bridge electrically connecting the first compute device to the second device stack.