Embedded Interconnection Bridge Package to Limit Warpage
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Solution Overview
Problem
Existing semiconductor packages using interposers face issues such as warpage, poor yield, high manufacturing costs, and difficulty in forming fine patterns, particularly when using silicon or organic interposers.
Innovation Solution
A semiconductor package design that incorporates a first connection structure with a redistribution layer directly on semiconductor chips, an interconnection bridge connected via a connection member, and a second connection structure embedding the bridge to provide electrical connections, reducing the need for conventional interposers and addressing warpage and yield issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon-based interposer is used to connect semiconductor chips, then electrical connectivity between chips is improved, but warpage occurs and manufacturing cost increases
Solution Approach 1:
The patent divides the interconnection function into separate components: connection pads on chips, bump electrodes for vertical connection, and trace patterns on the insulating substrate for horizontal connection. This segmentation eliminates the need for a rigid silicon interposer, reducing warpage while maintaining electrical connectivity between multiple semiconductor chips.
Solution Approach 2:
The patent introduces an insulating substrate as an intermediary carrier that replaces the silicon interposer. This substrate provides a flexible platform for mounting chips and routing traces, mediating the electrical connection between chips without causing the warpage issues associated with silicon interposers.
2Reliability
If a silicon-based interposer is used to connect semiconductor chips, then electrical connectivity between chips is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon interposers with a cost-effective insulating substrate that can be manufactured using standard PCB techniques. The use of conventional materials and processes significantly reduces manufacturing cost while achieving the required electrical connectivity function.
Solution Approach 2:
The patent changes the material parameter from silicon to insulating substrate materials (such as epoxy resin, polyimide, or ceramic), and changes the interconnection method from TSV-based to trace-pattern-based. These parameter changes enable the use of lower-cost manufacturing processes while maintaining electrical connectivity.
3Reliability
If an interposer is used to connect semiconductor chips, then chip interconnection is achieved, but yield decreases due to process issues
Solution Approach 1:
The patent replaces the complex mechanical TSV formation process with a simpler trace pattern deposition process on the insulating substrate. This substitution eliminates difficult-to-control steps such as TSV drilling, plating, and alignment, thereby improving manufacturing yield while achieving reliable chip interconnection.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the trace patterns and bump electrodes on the insulating substrate before chip mounting. This preliminary preparation simplifies the subsequent chip assembly process and reduces the risk of defects during final assembly, improving overall yield.
4Ease of operation
If a conventional interposer structure is used, then chip mounting is simplified, but fine pattern formation becomes difficult
Solution Approach 1:
The patent changes the substrate material parameter from silicon to insulating materials that are compatible with standard PCB fabrication processes. This enables the formation of fine trace patterns using conventional photolithography and etching techniques, achieving high manufacturing precision while simplifying chip mounting operations.
Data Source
AI summary
A semiconductor package includes a first connection structure having first and second surfaces and including a first redistribution layer, a first semiconductor chip disposed on the first surface and having a first connection pad electrically connected to the first redistribution layer, a second semiconductor chip disposed around the first semiconductor chip on the first surface and having a second connection pad electrically connected to the first redistribution layer, an interconnection bridge disposed on the second surface to be spaced apart from the second surface and connected to the first redistribution layer through a connection member to electrically connect the first and second connection pads to each other, and a second connection structure disposed on the second surface to embed the interconnection bridge and including a second redistribution layer electrically connected to the first redistribution layer.