Embedded Bridge TSV Interconnect Structure for Shorter Package Routing
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Solution Overview
Problem
Conventional 2.5D semiconductor packages face limitations in interconnect density and signal integrity due to the use of silicon interposers and C4 bumps, which result in increased global interconnect length and RC loading, affecting performance and power consumption.
Innovation Solution
A resin molded package substrate with an embedded bridge through-silicon-via (TSV) interconnect component, featuring metal vias and redistribution layers on both sides, which integrates a silicon substrate with TSVs and connecting elements to reduce interconnect length and enhance signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional silicon interposer with C4 bumps is used, then interconnect density is reduced, but global interconnect length increases and RC loading increases
Solution Approach 1:
The patent extracts and eliminates the conventional silicon interposer from the package structure. Instead of using a separate interposer substrate, the invention integrates the interconnect function directly into the package substrate through embedded bridge TSV interconnect components, thereby removing the source of excessive interconnect length and RC loading.
Solution Approach 2:
The patent embeds the bridge TSV interconnect component within the package substrate structure. The TSV interconnect component is nested inside the resin molded package substrate, creating a compact integrated structure that reduces overall interconnect length while maintaining high interconnect density.
2Quantity of substance
If conventional silicon interposer with C4 bumps is used, then interconnect density is reduced, but RC loading increases affecting power consumption
Solution Approach 1:
By removing the conventional silicon interposer, the patent eliminates the source of high RC loading that causes excessive power consumption. The embedded bridge TSV structure provides lower resistance and capacitance paths, directly reducing energy loss.
Solution Approach 2:
The patent changes the physical parameters of the interconnect structure by using TSV technology with smaller diameter and shorter length compared to C4 bumps. This parameter change results in reduced resistance and capacitance, thereby reducing RC loading and power consumption.
3Device complexity
If conventional silicon interposer is used, then device complexity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the interposer function with the package substrate into a single integrated structure. The bridge TSV interconnect component is combined with the package substrate layers, reducing the number of separate components and simplifying the overall device structure while maintaining manufacturing precision through integrated fabrication processes.
Data Source
AI summary
A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.