Embedded Bridge TSV Package Substrate for Shorter Die Interconnects
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Solution Overview
Problem
Conventional 2.5D semiconductor packages face limitations in interconnect density and signal integrity due to the use of silicon interposers and C4 bumps, which result in increased global interconnect length and RC loading, affecting performance and power consumption.
Innovation Solution
A resin molded package substrate with an embedded bridge through-silicon-via (TSV) interconnect component is introduced, featuring metal vias and redistribution layers on both sides of the substrate, along with a bridge TSV interconnect component that includes a silicon substrate with integrated TSVs and redistribution layers, connecting semiconductor dies directly and reducing the need for an interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2.5D semiconductor packages use silicon interposers with C4 bumps, then interconnect density is limited, but global interconnect length increases and RC loading increases
Solution Approach 1:
The patent extracts and eliminates the silicon interposer from the conventional 2.5D package architecture. By directly mounting multiple semiconductor dies on a single package substrate using micro-bumps, the design removes the intermediate interposer layer that caused increased global interconnect length and RC loading, thereby improving interconnect density while reducing overall interconnect length
Solution Approach 2:
The patent merges multiple semiconductor dies and the package substrate into a more integrated structure. By directly attaching multiple dies to the package substrate without an interposer, the design combines these components into a tighter integration scheme that reduces the number of interconnect layers and decreases global interconnect length
2Quantity of substance
If conventional 2.5D semiconductor packages use silicon interposers with C4 bumps, then interconnect density is limited, but power consumption increases
Solution Approach 1:
By removing the silicon interposer from the architecture, the patent eliminates the additional interconnect paths that contributed to RC loading. This extraction of the interposer component directly reduces the resistive and capacitive losses in the signal paths, thereby lowering power consumption while maintaining or improving interconnect density
Solution Approach 2:
The merged structure of multiple dies directly mounted on the package substrate creates shorter and more direct signal paths. This consolidation reduces the total interconnect length and the number of interfaces, which decreases RC loading and consequently reduces power consumption
3Reliability
If conventional 2.5D semiconductor packages use silicon interposers, then performance is enhanced, but form factor increases
Solution Approach 1:
By extracting the silicon interposer from the package architecture, the patent reduces the overall footprint and thickness of the device. This removal of the intermediate layer allows for a more compact form factor while maintaining performance through direct die-to-substrate connections that reduce signal path length and improve signal integrity
Data Source
AI summary
A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.