Embedded Silicon Bridge Via Pillars for High-Density SiP Interconnects
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Solution Overview
Problem
Existing technologies face challenges in reducing the size of interconnects between in-package devices in system-in-package (SiP) devices without compromising performance, particularly in computing devices like smartphones and tablets where space is limited.
Innovation Solution
The implementation of an embedded silicon bridge with tall via pillars and ganged via pillars, combined with photolithographic and semi-additive plating techniques, allows for high-density interconnects within organic substrates, eliminating the need for silicon interposers and enabling smaller geometries than conventional laser drilling can achieve.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional laser drilling is used to create vias, then via formation is achievable, but the geometry size is limited and cannot achieve smaller dimensions
Solution Approach 1:
The patent replaces mechanical laser drilling with a chemical etching process to form vias. The chemical etching allows for smaller via dimensions and better geometric control that cannot be achieved with conventional laser drilling, directly resolving the contradiction between manufacturing precision and ease of manufacture.
Solution Approach 2:
The patent changes the process parameters by using chemical etching instead of mechanical drilling, enabling via geometries with smaller dimensions and different aspect ratios. This parameter change allows achieving sub-10 micrometer via sizes while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
2Reliability
If silicon interposers are used for high-density interconnects, then interconnection performance is improved, but device size and complexity increase
Solution Approach 1:
The patent extracts and eliminates the silicon interposer component from the package structure. By forming high-density interconnects directly within the organic substrate using vertically stacked vias, the solution removes the need for separate silicon interposer layers, thereby reducing device complexity and overall package size while maintaining interconnection performance.
Solution Approach 2:
The patent transitions from planar interconnect routing to three-dimensional vertically stacked via structures. This dimensional change allows high-density interconnections to be achieved within the substrate plane without requiring additional lateral space for silicon interposers, effectively resolving the contradiction between performance and complexity.
3Quantity of substance
If via pillars are made taller to achieve higher density, then interconnect density is improved, but manufacturing difficulty and via aspect ratio challenges increase
Solution Approach 1:
The patent applies preliminary under-plating to via sidewalls before final via filling. This preliminary action creates a tapered via structure with wider opening than bottom, reducing the effective aspect ratio and improving manufacturability. The under-plating is performed as a preliminary step that facilitates subsequent via filling while maintaining control over the final via geometry.
Solution Approach 2:
The patent changes the via geometry parameters by creating tapered vias with controlled aspect ratios through chemical etching and under-plating. This allows achieving high interconnect density with taller via structures while maintaining manufacturing precision through controlled chemical processes rather than mechanical drilling, which cannot achieve the same level of geometric control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-density interconnects that support high-bandwidth memory interfaces and die-stitching, while minimizing size and maintaining performance, thus addressing the space constraints in compact computing devices.
Implementation Method 1
semi-additive plating techniques
Data Source
AI summary
An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.