Embedded Interconnect Bridges for Fine-Pitch Glass Package Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multi-die semiconductor packaging architectures face challenges with larger form factors, poor yield, and reliability issues due to warpage and alignment problems in traditional substrates, particularly in achieving fine die-to-die interconnections and high interconnect density.
Innovation Solution
The use of a glass patch architecture with hybrid bonded interconnects and embedded interconnect bridges allows for finer contact pitches and higher interconnect density, enabling device-level attachment of dies to the package substrate, reducing warpage susceptibility, and improving yield through low total thickness variation and high aspect ratio patterning capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional substrate architectures are used for multi-die integration, then die-to-die interconnections can be established, but the form factor increases and warpage issues occur
Solution Approach 1:
The substrate is segmented into a glass core layer and separate build-up layers, allowing independent optimization of each layer. The glass core provides dimensional stability while the build-up layers provide interconnect routing, resolving the contradiction between reliable interconnections and compact form factor.
Solution Approach 2:
The patent uses a composite substrate structure combining glass core with organic or inorganic build-up layers. This composite approach leverages the dimensional stability of glass while incorporating the routing flexibility of other materials, achieving both compact form factor and reliable interconnections.
2Ease of operation
If traditional organic build-up layers are used for interconnect routing, then signal connection between dies is achieved, but manufacturing precision deteriorates due to warpage
Solution Approach 1:
Different regions of the substrate have different properties: the glass core region provides dimensional stability for precise alignment, while the build-up layers provide routing flexibility. This local differentiation resolves the contradiction between ease of routing and manufacturing precision.
3Quantity of substance
If finer contact pitches are achieved through device-level attachment, then interconnect density increases, but manufacturing complexity increases
Solution Approach 1:
The substrate and build-up layers are prepared in advance with pre-defined routing patterns and contact locations. This preliminary preparation simplifies the final assembly process, allowing high interconnect density to be achieved without proportionally increasing manufacturing complexity.
Data Source
AI summary
A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.