Embedded Capacitance Layer for Power Integrity
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Solution Overview
Problem
Microelectronic devices face challenges with power supply integrity due to voltage drops and noise, particularly as device dimensions shrink and operating frequencies increase, leading to reduced tolerance for voltage drop and noise, which can cause functional failures.
Innovation Solution
A capacitance layer is formed on a silicon chip within a packaged device to filter the power supply, placing it as close as possible to active semiconductor devices, thereby minimizing voltage drop and noise, and improving power supply integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitance is located outside the packaged device, then large capacitances can be placed for optimum filtering capabilities, but trace lengths increase which reduces power supply signal integrity
Solution Approach 1:
The patent transitions the capacitance location from external (outside the package) to internal (within the package substrate), effectively moving the filtering component into a different spatial dimension relative to the power delivery path. This reduces the trace length between the power source and the filtering capacitance, improving power supply signal integrity while maintaining effective filtering capability.
2Reliability
If capacitance is located on the chip, then trace lengths are reduced improving power supply integrity, but valuable chip real-estate is consumed
Solution Approach 1:
The patent merges the capacitance layer with the power distribution network layers within the package substrate, creating an integrated structure where the capacitance is formed between adjacent power and ground planes. This integration approach provides effective power supply filtering while utilizing the existing package substrate space efficiently, avoiding the need for separate discrete capacitor components that would consume additional chip real-estate.
3Productivity
If device dimensions are shrunk and operating frequencies increased, then device performance is improved, but tolerance for voltage drop and noise decreases
Solution Approach 1:
The patent implements preliminary filtering action by placing the capacitance layer within the package substrate, close to the power entry point and before the power reaches the active devices. This preliminary filtering removes voltage drops and noise early in the power delivery path, protecting the sensitive high-frequency devices from power supply disturbances before they can affect device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise and voltage drop, maintaining the integrity of the power supply and ensuring reliable operation of circuits by filtering the power supply within the packaged device.
Implementation Method 1
Capacitance between power and ground distribution networks help to filter the power supply. For instance, capacitance between power and ground distribution networks act to store charge location, which helps to mitigate the voltage drop and noise of the power supply
Data Source
AI summary
System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply.