Multi-Layer Embedded Capacitance Substrate for Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing printed circuit board (PCB) technologies face challenges in miniaturization due to the limitations of pre-fired ceramic nano-powders, which result in irregular particle shapes, wide particle size distributions, and high sedimentation rates, making it difficult to achieve high-density patterns and thin dielectric layers that can withstand voltage without breakdown.
Innovation Solution
A method is developed to form capacitors and resistors within a substrate using a laser drillable, multi-layer embedded capacitance and resistance core substrate, where layers of resistance material with embedded conductive material are combined with high dielectric constant capacitance material, allowing for the creation of thin, high-capacitance layers without the need for an interim dielectric layer, and enabling the use of nano and micro particles for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pre-fired ceramic nano-powders are used to increase dielectric constant, then capacitance density is improved, but particle size distribution becomes wide and irregular, causing manufacturing difficulties
Solution Approach 1:
The patent changes the particle size parameter from wide distribution (500-20,000 nm) to narrow distribution (50-200 nm), and controls the dielectric constant through controlled hydrolysis and condensation processes rather than relying on pre-fired ceramic properties
Solution Approach 2:
The patent creates a composite dielectric material combining inorganic nanoparticles (metal titanates) with organic binder materials, where the inorganic phase provides high dielectric constant and the organic phase provides structural integrity and processability
2Quantity of substance
If dielectric layer thickness is reduced to increase capacitance per area, then capacitance density is improved, but voltage breakdown risk increases
Solution Approach 1:
The patent changes the dielectric strength parameter by using a composite material system where the organic binder provides electrical insulation and the inorganic nanoparticles provide high dielectric constant, achieving both thin layer capability and voltage resistance
Solution Approach 2:
The organic binder material acts as an intermediary between the inorganic nanoparticles, providing both structural support for thin layer formation and electrical insulation to prevent voltage breakdown while allowing the inorganic phase to provide high capacitance
3Quantity of substance
If higher dielectric constant materials are used to increase planar capacitance, then capacitance density is improved, but material processing difficulty increases
Solution Approach 1:
The patent changes the processing temperature parameter from high temperature (pre-fired ceramic) to low temperature (hydrolysis and condensation at room or moderate temperature), making the material easier to process while maintaining high dielectric constant
Solution Approach 2:
The patent utilizes phase transitions during sol-gel processing, where the precursor solution transitions to gel phase and then to solid dielectric layer, enabling easy processing of high dielectric constant materials without requiring high temperature sintering
4Quantity of substance
If nano-powders with wide particle size distribution are used, then dielectric constant is improved, but sedimentation rate increases
Solution Approach 1:
The patent changes the particle size parameter to a narrow, controlled range (50-200 nm) which reduces the sedimentation rate while maintaining high dielectric constant, overcoming the issue of rapid sedimentation associated with wide particle size distributions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of substrates with bulk decoupling capacitance and resistance, providing a wide range of capacitor and resistor values with low inductance and parasitics, allowing for miniaturization and efficient z-directional communication, while preventing voltage breakdown and flaking issues.
Implementation Method 1
At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material
Implementation Method 2
Thru-holes are formed by laser
Data Source
AI summary
A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.