Embedded Capacitive Stack for High-Density Decoupling
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Solution Overview
Problem
Existing circuit boards face challenges in providing sufficient decoupling capacitance, especially for high power, high switching speed IC devices, due to limited capacitance density and interference issues, and the manufacturing of stacked capacitive laminates with thin dielectric layers is complex, prone to defects, and costly.
Innovation Solution
A method for manufacturing a capacitive stack with high capacitive density using a planar core substrate with alternating thin dielectric and conductive layers, where the dielectric layers are tested for integrity before adding subsequent layers, and nanopowder-loaded dielectric materials are used to increase capacitance while maintaining structural rigidity and reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete bypass capacitors are used for high-frequency decoupling, then noise suppression and resonance dampening are improved, but board space is consumed and parasitic inductance is introduced
Solution Approach 1:
The patent merges the decoupling capacitor function directly into the PCB laminate structure by creating embedded capacitive elements between internal ground and power planes. This integration eliminates the need for separate discrete capacitors, thereby suppressing noise and resonance while conserving board space.
Solution Approach 2:
The patent introduces an intermediary embedded capacitive structure within the PCB laminate that acts as a mediator between power and ground planes. This embedded capacitance provides high-frequency decoupling without requiring external components, thus improving noise suppression while avoiding the parasitic inductance associated with discrete capacitor leads.
2Area of stationary object
If integrated capacitive laminates are used to provide embedded decoupling capacitance, then board space is saved, but sufficient capacitance for high power IC devices cannot be achieved
Solution Approach 1:
The patent transitions from two-dimensional surface-mounted capacitors to three-dimensional embedded capacitive structures within the PCB laminate. By utilizing internal layers and creating volumetric capacitive elements, the design achieves higher capacitance values without consuming additional board space, thereby satisfying the demands of high power IC devices.
Solution Approach 2:
The patent employs composite material structures within the PCB laminate, combining dielectric materials with conductive planes to create embedded capacitive elements. This composite approach enables higher capacitance density within the laminate structure, providing sufficient decoupling capacitance for high power devices while maintaining space efficiency.
3Ease of manufacture
If all devices are connected to the same embedded capacitive laminate, then manufacturing is simplified, but interference and noise between devices occur
Solution Approach 1:
The patent segments the embedded capacitive laminate into multiple isolated capacitive regions, each dedicated to specific devices or device groups. This segmentation prevents noise and interference from propagating between devices while maintaining the manufacturing advantages of an integrated embedded structure, as the isolation is achieved through design rather than separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a capacitive stack with increased capacitance density, reduces interference between devices, and allows for early detection of defects, thereby improving signal quality and reducing manufacturing costs and waste.
Implementation Method 1
A first conductive foil is coated with a second dielectric layer including an uncured or semi-cured dielectric material loaded with a nanopowder selected to achieve a desired dielectric constant
Implementation Method 2
an embedded decoupling capacitance (or buried capacitance) is typically used to eliminate the need for bypass capacitors mounted in the vicinity of each integrated circuit mounted to the board
Data Source
AI summary
A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.