Embedded Capacitor Circuit Board Layout Flexibility
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Solution Overview
Problem
Conventional circuit board structures with embedded capacitors face limitations in flexibility of layout and capacitance due to the use of whole high dielectric constant material layers, leading to waste, parasitic capacitance, and compromised layout flexibility, as well as difficulties in achieving parallel connections for increased capacitance.
Innovation Solution
A circuit board structure with capacitors embedded, comprising multiple core layers with dielectric layers and circuit layers on their surfaces, where capacitors are individually connected to the circuit layers on the same side, and adhesive layers and conductive through holes or vias are used to connect the circuit layers, allowing for improved layout flexibility and parallel capacitor connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a whole piece of high dielectric constant material layer is used within a packaging substrate, then capacitors can be formed between inner and outer electrode plates, but the unused part of the material layer causes waste and increases cost
Solution Approach 1:
The patent divides the high dielectric constant material layer into multiple separate capacitor units instead of using a single continuous layer. Each capacitor unit is independently formed with its own electrode plates and dielectric material, allowing precise control over material usage and eliminating waste from unused portions.
Solution Approach 2:
The patent applies high dielectric constant material only in specific locations where capacitors are needed, rather than using a continuous layer across the entire substrate. This localized application ensures material is used efficiently only where functional requirements demand it.
2Quantity of substance
If a whole piece of high dielectric constant material layer is used, then capacitors can be formed, but the unused part contacts circuits causing parasitic capacitance that interferes with electrical qualities
Solution Approach 1:
By segmenting the dielectric material into discrete capacitor units separated by low dielectric constant material, the patent prevents unwanted electrical interaction between capacitor units and surrounding circuits, thereby eliminating parasitic capacitance effects.
Solution Approach 2:
The patent introduces a low dielectric constant material layer between the high dielectric constant material units and surrounding circuits. This intermediary material acts as an electrical insulator that prevents parasitic capacitance formation while allowing the high dielectric constant material to function effectively within capacitors.
3Device complexity
If electrode plates and circuits are laid together in a circuit layer, then integration is achieved, but the flexibility of layouts of both electrode plates and circuits is compromised
Solution Approach 1:
The patent separates electrode plates from circuit layers by placing capacitors in a dedicated intermediate layer between the circuit layer and ground reference. This dimensional separation allows independent optimization of circuit layout and capacitor placement, restoring layout flexibility while maintaining integration.
Solution Approach 2:
The patent embeds capacitor structures within the multi-layer board structure, nesting them between circuit layers rather than placing them on the same plane. This nested arrangement allows circuits and capacitors to coexist in different spatial dimensions, providing both integration and layout flexibility.
4Quantity of substance
If high dielectric constant material is laminated between copper layers, then capacitors can be formed, but the poor fluidity of the material causes voids and poor uniformity of thickness
Solution Approach 1:
The patent changes the physical state and processing parameters of the high dielectric constant material by providing it as a slurry or paste rather than a rigid block. This allows the material to flow and conform to the mold cavity, ensuring uniform thickness and eliminating voids through proper rheological control during lamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility of circuit layouts, enables parallel connections for increased capacitance, and optimizes the use of inner space, leading to miniaturization and reduced costs by minimizing waste and parasitic capacitance.
Implementation Method 1
High dielectric constant material is laminated between two copper layers and then electrode plates and circuits are formed to fabricate capacitors
Implementation Method 2
The core substrate 10 and the carrier 2 are bonded together by an adhesive layer 5
Implementation Method 3
The inner circuit layer 11 and the outer circuit layer 13 as well as the circuits on two sides of the substrate are electro-connected by plated through holes (PTH) 14
Data Source
AI summary
A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.