Embedded Capacitive Module with Co-Coupling Vias for Inductance Reduction
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Solution Overview
Problem
Decoupling capacitors, especially surface-mounted devices (SMD) and embedded capacitors in PCBs or IC substrates, face challenges in stabilizing power supply at high frequencies due to increased parasitic inductance, leading to degradation of decoupling performance and limited board space.
Innovation Solution
A capacitive module with multiple stacked capacitors and conductive planes, where each capacitor is electrically coupled through conductive vias to power and ground planes, reducing inductance by canceling out magnetic flux and providing multi-capacitance for different frequency noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If SMD decoupling capacitors are used, then board space is occupied, but parasitic inductance increases at high frequencies
Solution Approach 1:
The patent transitions from two-dimensional SMD capacitor placement on PCB surface to three-dimensional embedded capacitor structures within the PCB layers. Multiple capacitor elements are stacked vertically across different PCB layers, utilizing the Z-dimension to reduce parasitic inductance while maintaining compact footprint.
Solution Approach 2:
The patent embeds capacitor structures within the PCB substrate itself, nesting multiple capacitor elements within the same physical space. Conductive vias and electrode patterns are nested across multiple PCB layers, creating a compact multi-layer capacitor assembly that reduces both inductance and board space occupation.
2Area of stationary object
If embedded capacitors are used, then board space is reduced, but impedance increases at frequencies greater than resonant frequency
Solution Approach 1:
The patent divides the embedded capacitor into multiple discrete capacitor elements distributed across different PCB layers. Each capacitor element is connected through conductive vias, creating a segmented structure that reduces overall parasitic inductance and extends the effective decoupling bandwidth beyond the resonant frequency of individual elements.
Solution Approach 2:
The patent combines multiple capacitor elements with different capacitance values and resonant frequencies into a single integrated embedded structure. This merging of parallel capacitor paths creates a composite decoupling network that maintains low impedance across a broader frequency range than individual capacitors alone.
3Reliability
If multiple conductive vias are used to couple capacitors to power and ground planes, then inductance is reduced through magnetic flux cancellation, but device complexity increases
Solution Approach 1:
The patent employs asymmetric arrangements of conductive vias with respect to the capacitor electrodes, positioning vias to optimize magnetic flux cancellation paths. The via locations and configurations are deliberately asymmetric to create opposing current loops that cancel inductive effects, achieving low inductance without requiring symmetric complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces impedance and broadens decoupling bandwidth, enhancing power integrity by stabilizing power supply and optimizing board space utilization.
Implementation Method 1
reducing inductance by canceling out magnetic flux
Data Source
AI summary
A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via. Furthermore, the capacitive module may include a first conductive plane being electrically coupled to a first plane with a first polarity through one of the at least one first conductive via and a second conductive plane being electrically coupled to a second plane with a second polarity, opposite to the first polarity, through one of the at least one second conductive via.