Embedded Capacitor ESR Reduction via Exposed Portion Optimization
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in reducing equivalent series resistance (ESR) while preventing delamination, as increasing the electrode exposure area weakens adhesion between the electrode and dielectric layers, leading to potential delamination during laminate cutting.
Innovation Solution
The electronic component incorporates capacitor conductors with exposed portions between insulating layers, with external electrodes plated to cover these portions, optimizing the length of exposed portions to 35-45% of the insulating layer's outer periphery to reduce ESR and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the area of the electrode exposed from the bottom surface of the laminate is increased to reduce ESR, then the equivalent series resistance is reduced, but delamination between the dielectric layers and electrode is likely to occur
Solution Approach 1:
The patent optimizes the exposed portion length of capacitor conductors to a specific range (35-45% of the insulating layer's outer periphery length) to achieve the best balance between reducing ESR and preventing delamination. This parameter optimization resolves the contradiction by finding the optimal exposure dimension that satisfies both requirements.
2Loss of energy
If the area of the electrode exposed from the bottom surface of the laminate is increased to reduce ESR, then the connection area between electrode and terminal is increased, but delamination may occur during cutting of the laminate
Solution Approach 1:
The patent specifies that the exposed portion length of capacitor conductors should be 35-45% of the insulating layer's outer periphery length. This parameter control ensures sufficient ESR reduction while maintaining structural integrity during cutting operations, preventing delamination that would occur with larger exposed areas.
3Loss of energy
If the exposed portion length of capacitor conductors is increased to reduce ESR, then the ESR is reduced, but the adhesion between electrode and dielectric layer becomes weaker
Solution Approach 1:
The patent determines through experimentation and analysis that the exposed portion length of capacitor conductors should be controlled within 35-45% of the insulating layer's outer periphery length. This optimized parameter range achieves effective ESR reduction (10% or more) while preventing delamination, resolving the contradiction between ESR reduction and adhesion strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces ESR by 10% or more and prevents delamination, maintaining structural integrity during cutting and operation.
Implementation Method 1
a first external electrode provided on the surface of the laminate by plating to directly cover the first exposed portion, and a second external electrode provided on the surface of the laminate by plating to directly cover the second exposed portion
Data Source
AI summary
A laminate includes insulating layers laminated to each other. Capacitor conductors are embedded in the laminate and have exposed portions exposed between the insulating layers at respective surfaces of the laminate. The capacitor conductors define a capacitor. External electrodes are provided by plating on the respective surfaces of the laminate so as to directly cover the respective exposed portions. When the laminate is viewed in plan in a y axis direction, the length of each of the exposed portions is approximately 35% to approximately 45% of the length of an outer periphery of the insulating layer.