Embedded Capacitor Circuit Board Layout for Lamination Accuracy
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Solution Overview
Problem
Small-sized embedded capacitors in circuit boards are prone to deviation during lamination due to material flow, leading to functional abnormalities and difficulty in electrical connection with circuit layers.
Innovation Solution
A circuit board design that integrates a dielectric layer with electrodes, where the dielectric layer is physically connected to a substrate, and electrodes are formed using a mask etching process, allowing for precise positioning and reduced size, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the embedded capacitor size is reduced, then the degree of integration is improved, but the positional accuracy deteriorates due to deviation during lamination
Solution Approach 1:
The embedded capacitor is divided into separate components: a dielectric layer and electrode layers, which are independently formed and then assembled. This segmentation allows precise positioning of each component without relying on the integrity of a single monolithic structure during lamination, thereby maintaining positional accuracy while enabling small sizes for high integration.
Solution Approach 2:
The dielectric layer and electrode layers are pre-formed and positioned on the substrate before final assembly. The dielectric layer is formed in a first region and electrode layers in second and third regions, with preliminary positioning structures (such as alignment marks or mechanical features) that ensure accurate alignment during subsequent lamination, preventing deviation even when the capacitor is small.
2Productivity
If the embedded capacitor size is reduced, then the degree of integration is improved, but the electrical connection difficulty increases due to small-sized pads
Solution Approach 1:
The electrode layers are designed with non-uniform characteristics: the regions forming the capacitor electrodes have different properties from the connection pad regions. The connection pads are specifically engineered with larger area and optimized geometry in the fourth region, while the capacitor electrodes in second and third regions maintain compact dimensions. This local differentiation allows small overall capacitor size while providing adequately sized pads for reliable electrical connection.
Solution Approach 2:
The solution moves from a two-dimensional planar capacitor design to a three-dimensional structure with vertical stacking of dielectric and electrode layers. This dimensional transition allows the capacitor to achieve small footprint area while maintaining functional requirements, and the connection pads can be positioned in optimal locations for electrical connection without being constrained by the compact planar layout.
3Device complexity
If the lamination process is used to bury the embedded capacitor, then the manufacturing process is simplified, but the positional accuracy deteriorates due to impact of flowing material
Solution Approach 1:
A release layer or release film is introduced as an intermediary between the dielectric layer and the upper substrate during lamination. This release layer prevents direct contact and potential contamination or deformation between the flowing material and the precision components (dielectric and electrode layers), allowing the lamination process to proceed simply while protecting the positional accuracy of the embedded capacitor.
Solution Approach 2:
Protective structures such as alignment marks, mechanical features, or cushioning layers are provided beforehand to protect the dielectric and electrode layers from impact and deformation during the lamination process. These protective measures are built into the structure prior to assembly, preventing material flow from causing positional deviation while maintaining the simplicity of the lamination manufacturing process.
Data Source
AI summary
A provided circuit board includes an embedded capacitor, a substrate, and an insulating layer. The embedded capacitor includes a dielectric layer, a first electrode and a second electrode. The dielectric layer has a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface, and a fourth side surface opposite to the second side surface. The first and second electrodes respectively cover the first and third side surfaces. The substrate surrounds the embedded capacitor and is physically connected to the second and fourth side surfaces. The first electrode is between the first side surface and a sidewall of the substrate. The insulating layer covers the embedded capacitor and the substrate and extends from an upper surface to a lower surface of the substrate along the first electrode and the sidewall of the substrate.