Embedded Capacitor Layer for Low Impedance Power Delivery

The patent combines the capacitor structure with the circuit substrate by forming the first metal layer, dielectric layer, and second metal layer directly on the substrate. This integration merges the capacitor function into the substrate itself, reducing electromagnetic noise interference without requiring separate discrete capacitor components, thus resolving the contradiction between simplifying the overall structure and reducing harmful electromagnetic effects.

The patent utilizes the vertical dimension by stacking the first metal layer, dielectric layer, and second metal layer in multiple layers on the substrate. This three-dimensional arrangement creates a low-impedance path for transient current supply and effectively suppresses electromagnetic noise by confining the electric field within the capacitor structure, thereby reducing harmful electromagnetic radiation without increasing planar footprint.

The patent transitions from a planar power supply layout to a multi-layer vertical structure. The first metal layer connected to the power supply terminal and the second metal layer connected to ground are stacked vertically with the dielectric layer in between, creating a low-impedance path for transient current. This vertical arrangement reduces the current path length and impedance, improving transient current supply efficiency while maintaining manufacturing feasibility through standard thin-film deposition processes.

The patent changes the geometric parameters of the capacitor structure by making the first and second metal layers extend beyond the dielectric layer boundaries. This parameter adjustment creates overlapping regions that reduce impedance by increasing the effective area for current flow, thereby improving transient current supply efficiency. The extended metal layers also provide better electrical connection to external terminals while maintaining a compact overall structure.