Semiconductor Module Layout With Embedded Decoupling Capacitor

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Solution Overview

Problem

The increasing malfunctions in semiconductor apparatuses due to power supply potential fluctuations caused by external and self-noise, which are exacerbated by the limited space for capacitors on printed circuit boards, leading to enlarged boards and reduced power supply impedance.

Innovation Solution

An electronic module design where a chip component, such as a multilayer ceramic capacitor, is positioned between the leads and the printed wiring board, reducing the inductance components and power supply impedance without increasing the module's size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a capacitor is added in the vicinity of the semiconductor apparatus to reduce power supply impedance, then the power supply impedance is reduced, but the printed circuit board size must be enlarged due to limited space

Engineering Contradiction:
Improvepower supply impedanceVSAvoidprinted circuit board area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention transitions from planar arrangement to three-dimensional arrangement by placing the capacitor between the semiconductor apparatus and the printed circuit board, utilizing the vertical dimension. This allows the capacitor to be positioned close to the power supply terminal without increasing the board's footprint, thereby reducing power supply impedance while maintaining compact board size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor is nested within the vertical space between the semiconductor apparatus package body and the printed circuit board. This nesting approach utilizes the available vertical clearance, allowing the capacitor to be integrated into the existing structure without requiring additional lateral space on the board.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If a capacitor is placed away from the semiconductor apparatus to avoid space constraints, then the printed circuit board size is reduced, but the power supply impedance reduction effect is diminished

Engineering Contradiction:
Improveprinted circuit board areaVSAvoidpower supply impedance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The invention resolves this contradiction by utilizing the vertical dimension to position the capacitor close to the semiconductor apparatus. By standing the capacitor upright between the apparatus and the board, the design achieves both compact board layout and effective noise suppression without compromising the impedance reduction benefit.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the package body height is increased to accommodate the capacitor between the board and leads, then the capacitor can be positioned optimally, but the semiconductor component size increases

Engineering Contradiction:
Improvecapacitor positioningVSAvoidpackage body height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The invention changes the mounting orientation and position parameters of the capacitor rather than increasing package height. By positioning the capacitor vertically between the board and leads, the design achieves optimal capacitor placement using the existing vertical clearance, avoiding the need to increase the semiconductor package dimensions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260032822A1Electronic module
Publication Date: 2026.01.29 CANON KK
  • US20260032822A1 patent drawing
  • US20260032822A1 patent drawing
  • US20260032822A1 patent drawing

AI summary

An electronic module includes: a printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead soldered to the printed wiring board, respectively; and a chip component, wherein the chip component is arranged between the printed wiring board and at least one of the first lead and the second lead, and wherein a portion of a package body of the semiconductor component is lower than a height of the chip component.