Embedded Silicon Capacitor Package Layout for Low-Impedance Power Delivery

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Solution Overview

Problem

Semiconductor packages with embedded capacitors face challenges in achieving high device density and performance while maintaining a compact size, as traditional capacitors increase the package size and impedance, affecting power delivery and noise control.

Innovation Solution

Incorporating integrated silicon capacitors (ISCs) within the dielectric layer of the redistribution layer in semiconductor packages, allowing for a low-profile, high-capacitance-density decoupling solution that reduces package size and improves power delivery and noise control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional capacitors are used in semiconductor packages, then power delivery and noise control are improved, but package size increases

Engineering Contradiction:

Improvepower delivery and noise controlVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The capacitor is merged with the redistribution layer structure, embedding it within the dielectric layers and wiring patterns of the redistribution layer. This integration allows the capacitor to share the same structural space as the redistribution layer, eliminating the need for separate capacitor components and reducing overall package size while maintaining power delivery and noise control functions

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The capacitor is nested within the redistribution layer by positioning it between dielectric layers and surrounding it with wiring patterns. The capacitor structure is contained within the vertical and horizontal boundaries of the redistribution layer, allowing multiple functional elements to occupy the same spatial envelope and reduce the package footprint

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If capacitor size is reduced to maintain compact package, then package size is reduced, but impedance increases affecting power delivery

Engineering Contradiction:

Improvepackage sizeVSAvoidimpedance and power delivery

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The capacitor is positioned locally within the redistribution layer at strategic locations close to high-power consuming regions. By optimizing the local placement of the capacitor within the redistribution layer structure, the design achieves effective noise control and power delivery to specific areas without requiring a large overall package size

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The capacitor design utilizes the vertical dimension by embedding it between dielectric layers of the redistribution layer. This vertical stacking approach allows the capacitor to achieve sufficient capacitance value without increasing the horizontal footprint, thereby maintaining low impedance for power delivery while keeping the package compact

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250015018A1Semiconductor device including semiconductor package with capacitor embedded in dielectric layer

Publication Date: 2025.01.09 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a semiconductor package which includes: a redistribution layer including at least one insulation layer in which a plurality of wiring patterns are formed; a semiconductor chip, on the redistribution layer, connected to at least one of the plurality of wiring patterns; and a capacitor disposed in the redistribution layer.