Embedded Capacitor Package Substrate for Compact Power Delivery
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Solution Overview
Problem
Integrated circuit device packages face challenges with capacitor placement due to limited routing space and socket constraints, leading to complications in power delivery and increased board space requirements as devices shrink in size.
Innovation Solution
Embedding capacitors within the package substrate, allowing for better use of vacant space and reducing the overall system height, while enabling conventional and cost-effective surface mount capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are placed on the die side or land side of the package, then power delivery is enabled, but available space is constrained by routing and socket limitations
Solution Approach 1:
The patent transitions capacitor placement from traditional two-dimensional surface mounting (die side or land side) to three-dimensional embedding within the package substrate. By creating vias through the substrate and placing capacitors in the internal space, the invention utilizes the z-dimension (vertical depth) to accommodate capacitors without increasing the package footprint, thereby resolving the space constraint while maintaining power delivery functionality
2Volume of moving object
If devices and packages are shrunk in size, then integration density is improved, but capacitor real estate and placement options become more problematic
Solution Approach 1:
The patent implements nesting by placing capacitors inside the package substrate structure itself. The capacitors are embedded within the substrate's internal volume, nested among the routing layers and structural elements. This allows the package to maintain a compact external size while accommodating capacitors in the internal three-dimensional space, effectively decoupling package footprint from capacitor accommodation capability
3Area of stationary object
If capacitors are removed from device packages and placed on the printed circuit board, then package space is freed, but board space requirements and complexity increase
Solution Approach 1:
The patent merges the package substrate and capacitor assembly into a single integrated structure. By embedding the capacitors within the package substrate and establishing electrical connections through internal vias, the invention combines what were previously separate components (package and capacitors) into one unified assembly. This integration eliminates the need for separate capacitor placement on the PCB, reducing both board space requirements and system complexity while maintaining all necessary power delivery functions
Data Source
AI summary
An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.