Embedded Capacitor Structures in Semiconductor Package Substrates
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, poor thermal performance, decreased reliability, and large size due to the conventional assembly approach of mounting passive components laterally adjacent to the semiconductor die, which limits the increase in total capacitance value and package size.
Innovation Solution
The integration of capacitor structures within or as part of lid or stiffener components using 3D printing techniques, allowing for higher capacitance without increasing substrate size, and providing both capacitive and enclosure or stiffener functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive components are mounted laterally adjacent to the semiconductor die on the package substrate, then the assembly approach is simple and components are easily installed, but the substrate space is consumed and the overall package size increases significantly
Solution Approach 1:
The patent merges the passive component mounting function with the package substrate structure itself by forming capacitive structures directly within the substrate layers. Multiple conductive layers and dielectric layers are integrated into the substrate to create capacitors, eliminating the need for separate discrete capacitor components and their dedicated mounting space.
Solution Approach 2:
The patent transitions from two-dimensional lateral mounting of passive components on the substrate surface to three-dimensional integration within the substrate volume. Capacitive structures are formed by stacking conductive and dielectric layers vertically within the substrate, utilizing the Z-dimension to achieve high capacitance values without increasing the substrate footprint.
2Quantity of substance
If the total capacitance value per package is increased using conventional assembly approaches, then higher capacitance is achieved, but the package size grows significantly
Solution Approach 1:
The patent implements nested structures by placing multiple conductive layers and dielectric layers within each other in a stacked configuration. Capacitive structures are nested within the substrate layers, with inner conductive layers surrounded by dielectric layers, which are in turn surrounded by outer conductive layers, maximizing capacitance density within the substrate volume.
Solution Approach 2:
The patent uses composite structures combining multiple conductive materials and dielectric materials in layered configurations. The capacitive structures are formed by stacking different materials with complementary properties, creating high-capacitance composite structures that fit within the substrate without increasing package volume.
3Quantity of substance
If multiple discrete capacitors are mounted on the substrate, then the required capacitance value is achieved, but the bill-of-material count increases and assembly yield decreases
Solution Approach 1:
The patent makes the package substrate multi-functional by giving it both its structural support function and its capacitive storage function. The substrate simultaneously serves as the mechanical foundation for mounting the semiconductor die and as the housing for integrated capacitive structures, eliminating the need for separate capacitor components and reducing the overall component count.
Solution Approach 2:
The patent combines the substrate structure with capacitive functionality by forming conductive and dielectric layers directly within the substrate during manufacturing. This integration merges what were previously separate functions (substrate support and capacitor storage) into a single unified structure, reducing bill-of-material counts and simplifying assembly.
Data Source
AI summary
A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.