Embedded Capacitor Die Layout for Close-Coupled PHY Decoupling
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Solution Overview
Problem
Existing on-die decoupling approaches using metal-insulator-metal (MIM) capacitors face deficiencies due to die floor planning, architectural design, and area constraints, leading to inadequate power delivery performance, while package level decoupling capacitors are often too far away from PHY areas to effectively address high-frequency noise in complex die architectures.
Innovation Solution
Embedding MIM capacitor dies within the package substrate in close proximity to surface mount dies, allowing for configurable capacitance and direct connections to power delivery interface circuitry, thereby enhancing power delivery performance and reducing noise impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If on-die MIM capacitors are used for decoupling, then high-frequency noise is reduced, but die area increases and floor planning becomes constrained
Solution Approach 1:
The capacitor function is extracted from the die itself and placed externally in the package substrate. The die no longer needs to contain MIM capacitors, freeing up die area while the capacitor functionality is provided by separate capacitor structures embedded in the package substrate nearby.
Solution Approach 2:
The decoupling capacitance is moved from the two-dimensional die surface to the three-dimensional package substrate volume. Capacitor structures are embedded in multiple layers of the package substrate, utilizing vertical space and intermediate layers to provide capacitance close to the die without consuming die area.
2Area of moving object
If package level decoupling capacitors are used, then die area is preserved, but distance to PHY areas increases reducing effectiveness
Solution Approach 1:
Capacitor structures are embedded in intermediate layers and multiple levels of the package substrate, positioning them vertically and horizontally closer to the PHY areas of the die. This multi-layer embedding reduces the effective distance for decoupling while maintaining die area preservation.
Solution Approach 2:
Capacitor structures are strategically positioned in specific locations within the package substrate that are locally optimal for decoupling different PHY areas. The package substrate is differentiated into regions with different capacitor densities and configurations matched to the local power delivery needs of underlying die regions.
3Reliability
If die-side capacitors are positioned close to PHY areas, then power delivery performance improves, but complex die architectures prevent adequate positioning
Solution Approach 1:
The decoupling capacitor function is extracted from the complex die architecture and implemented in the simpler package substrate environment. This avoids the floor planning and architectural constraints of the die while maintaining close coupling to PHY areas through strategic package substrate layout.
Solution Approach 2:
The package substrate serves as an intermediary between the die and the decoupling capacitors. It provides a flexible platform for positioning capacitor structures close to PHY areas without being constrained by die architecture, while still maintaining electrical connection to the die through controlled impedance traces and vias.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves power delivery performance by providing effective decoupling capacitance close to PHY areas, reducing AC resonance impedance, and addressing capacitance deficiencies in complex die architectures without increasing die size or cost.
Implementation Method 1
Embedding MIM capacitor dies within the package substrate in close proximity to surface mount dies, allowing for configurable capacitance and direct connections to power delivery interface circuitry
Data Source
AI summary
A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.