Embedded Capacitor Semiconductor Package for Stable Power Delivery
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing parasitic inductance and resistance, which affect the reliable power supply to semiconductor chips, particularly between circuit layers containing transistors and capacitors.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with a capacitor positioned between the circuit layer and the power distribution interconnection layer, and a second semiconductor chip with an insulating layer, both integrated with penetration vias and interconnection layers to minimize noise issues and enhance power stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor is positioned close to the penetration via to reduce parasitic inductance, then the power supply reliability is improved, but the parasitic capacitance between the capacitor and penetration via increases causing noise interference
Solution Approach 1:
The patent applies local quality by creating different functional zones around the penetration via. The first region has a first capacitance value while the second region has a second capacitance value, with the third region (between capacitor and penetration via) having a controlled capacitance value that is smaller than both first and second regions. This localized differentiation reduces parasitic capacitance in the critical coupling path while maintaining necessary capacitance for power stability in other areas.
Solution Approach 2:
The patent introduces a vertical dimension to the capacitor arrangement by forming capacitors at different depths within the semiconductor substrate. The first capacitor is positioned at a first depth and the second capacitor at a second depth, creating a three-dimensional distribution that reduces parasitic coupling while maintaining effective power supply decoupling functionality.
2Object-generated harmful factors
If the capacitor is spaced apart from the penetration via to reduce noise interference, then the noise interference is reduced, but the parasitic inductance and resistance increase affecting power supply stability
Solution Approach 1:
The patent employs nesting by positioning capacitors within the semiconductor substrate in a hierarchical structure. The capacitors are embedded at different depths (first depth and second depth) within the substrate, creating a nested three-dimensional arrangement that minimizes parasitic inductance and resistance while maintaining electrical isolation to reduce noise interference.
Solution Approach 2:
The patent changes the spatial parameters of capacitor positioning by controlling the capacitance values in different regions. The third region between the capacitor and penetration via has a capacitance value smaller than both the first and second regions, optimizing the balance between reducing parasitic inductance and minimizing noise coupling through parameter optimization.
3Reliability
If multiple capacitors are positioned at different depths to reduce parasitic inductance and resistance, then the power supply stability is improved, but the device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension within the semiconductor substrate to position multiple capacitors at different depths. This three-dimensional arrangement allows multiple capacitors to be integrated within the substrate volume without significantly increasing lateral footprint or interconnection complexity, as the capacitors are embedded within the existing substrate structure rather than requiring separate packaging.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a first semiconductor chip, which includes: a first semiconductor substrate having a first surface and a second surface, which are opposite to each other; a circuit layer on the first surface; a first interconnection layer on the circuit layer; a second interconnection layer on the second surface; a penetration via extending from the second surface into the first semiconductor substrate; and a capacitor extending from the second surface toward the first surface. The capacitor is spaced apart from the penetration via in a first direction that is parallel to the first surface of the first semiconductor substrate.